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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id z26sm839164oih.16.2019.08.29.12.25.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2019 12:25:51 -0700 (PDT) Date: Thu, 29 Aug 2019 14:25:50 -0500 From: Rob Herring To: Chunfeng Yun Cc: Kishon Vijay Abraham I , Mark Rutland , Matthias Brugger , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 02/11] dt-bindings: phy-mtk-tphy: make the ref clock optional Message-ID: <20190829192550.GA29881@bogus> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Aug 23, 2019 at 03:00:09PM +0800, Chunfeng Yun wrote: > Make the ref clock optional, then we no need refer to a fixed-clock > in DTS anymore when the clock of USB3 PHY comes from oscillator > directly > > Signed-off-by: Chunfeng Yun > --- > .../devicetree/bindings/phy/phy-mtk-tphy.txt | 13 +++++++------ > 1 file changed, 7 insertions(+), 6 deletions(-) > > diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > index d5b327f85fa2..1c18bf10b2fe 100644 > --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > @@ -34,12 +34,6 @@ Optional properties (controller (parent) node): > > Required properties (port (child) node): > - reg : address and length of the register set for the port. > -- clocks : a list of phandle + clock-specifier pairs, one for each > - entry in clock-names > -- clock-names : must contain > - "ref": 48M reference clock for HighSpeed analog phy; and 26M > - reference clock for SuperSpeed analog phy, sometimes is > - 24M, 25M or 27M, depended on platform. > - #phy-cells : should be 1 (See second example) > cell after port phandle is phy type from: > - PHY_TYPE_USB2 > @@ -48,6 +42,13 @@ Required properties (port (child) node): > - PHY_TYPE_SATA > > Optional properties (PHY_TYPE_USB2 port (child) node): > +- clocks : a list of phandle + clock-specifier pairs, one for each > + entry in clock-names > +- clock-names : may contain > + "ref": 48M reference clock for HighSpeed anolog phy; and 26M > + reference clock for SuperSpeed anolog phy, sometimes is > + 24M, 25M or 27M, depended on platform. How do you know the frequency when it is not present? > + > - mediatek,eye-src : u32, the value of slew rate calibrate > - mediatek,eye-vrt : u32, the selection of VRT reference voltage > - mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage > -- > 2.23.0 >