Re: [PATCH] perf/x86/intel: Update ICL Core and Package C-state event counters

[Peter Zijlstra <peterz@infradead.org>]

On Fri, Jul 26, 2019 at 05:08:46PM +0800, Harry Pan wrote:
> Ice Lake microarchitecture inherits Cannon Lake, it has CC1/PC8/PC9/PC10
> residency counters.
> 
> Update the list of Ice Lake PMU event counters from the snb_cstates[] list
> of events to the cnl_cstates[] list of events, which keeps all previously
> supported events and also adds the CORE_C1, PKG_C8, PKG_C9, and PKG_C10
> residency counters.
> 
> This benefits users to profile them through the perf interface.
> 
> Signed-off-by: Harry Pan <harry.pan@intel.com>
> 
> ---
> 
>  arch/x86/events/intel/cstate.c | 26 ++++++++++++++------------
>  1 file changed, 14 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
> index 688592b34564..08291233f5c9 100644
> --- a/arch/x86/events/intel/cstate.c
> +++ b/arch/x86/events/intel/cstate.c
> @@ -40,51 +40,53 @@
>   * Model specific counters:
>   *	MSR_CORE_C1_RES: CORE C1 Residency Counter
>   *			 perf code: 0x00
> - *			 Available model: SLM,AMT,GLM,CNL
> + *			 Available model: SLM,AMT,GLM,CNL,ICL
>   *			 Scope: Core (each processor core has a MSR)
>   *	MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
>   *			       perf code: 0x01
>   *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
> -						CNL
> +						CNL,ICL

That has a missing * introduced by the last such patch. Please take this
opportunity to put it back in.