[PATCH 0/2] OpenRISC ethoc device tree fixes

[PATCH 0/2] OpenRISC ethoc device tree fixes

[Stafford Horne]

These patches fix up and add ethoc device support to the OpenRISC device tree
definitions.  These have been confirmed to work with qemu and can be tested as
described on the qemu wiki:

  https://wiki.qemu.org/Documentation/Platforms/OpenRISC

I plan to submit during the 5.4 merge window.

Stafford Horne (2):
  or1k: dts: Fix ethoc network configuration in or1ksim devicetree
  or1k: dts: Add ethoc device to SMP devicetree

 arch/openrisc/boot/dts/or1ksim.dts    | 5 +++--
 arch/openrisc/boot/dts/simple_smp.dts | 6 ++++++
 2 files changed, 9 insertions(+), 2 deletions(-)

-- 
2.21.0

[PATCH 1/2] or1k: dts: Fix ethoc network configuration in or1ksim devicetree

[Stafford Horne]

This fixes several issues with the ethoc network device config.

Fisrt off, the compatible property used an obsolete compatibility
string; this caused the initialization to be skipped.  Next, the
register map was not given enough space to allocate ring descriptors,
this caused module initialization to abort.  Finally, we need to mark
this device as big-endian as needed by openrisc.

This was tested by me in qemu, the setup is documented on the qemu wiki:

  https://wiki.qemu.org/Documentation/Platforms/OpenRISC

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/boot/dts/or1ksim.dts | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/openrisc/boot/dts/or1ksim.dts b/arch/openrisc/boot/dts/or1ksim.dts
index d8aa8309c9d3..c0cb74e52f95 100644
--- a/arch/openrisc/boot/dts/or1ksim.dts
+++ b/arch/openrisc/boot/dts/or1ksim.dts
@@ -49,8 +49,9 @@
 	};
 
 	enet0: ethoc@92000000 {
-		compatible = "opencores,ethmac-rtlsvn338";
-		reg = <0x92000000 0x100>;
+		compatible = "opencores,ethoc";
+		reg = <0x92000000 0x800>;
 		interrupts = <4>;
+		big-endian;
 	};
 };
-- 
2.21.0

[PATCH 2/2] or1k: dts: Add ethoc device to SMP devicetree

[Stafford Horne]

This patch adds the ethoc device configuration to the OpenRISC basic SMP
device tree config.  This was tested with qemu.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/boot/dts/simple_smp.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/openrisc/boot/dts/simple_smp.dts b/arch/openrisc/boot/dts/simple_smp.dts
index defbb92714ec..71af0e117bfe 100644
--- a/arch/openrisc/boot/dts/simple_smp.dts
+++ b/arch/openrisc/boot/dts/simple_smp.dts
@@ -60,4 +60,10 @@
 		clock-frequency = <20000000>;
 	};
 
+	enet0: ethoc@92000000 {
+		compatible = "opencores,ethoc";
+		reg = <0x92000000 0x800>;
+		interrupts = <4>;
+		big-endian;
+	};
 };
-- 
2.21.0