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Mon, 02 Sep 2019 06:38:47 -0700 (PDT) Received: from localhost ([212.187.182.166]) by smtp.gmail.com with ESMTPSA id t18sm11645053wrx.76.2019.09.02.06.38.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Sep 2019 06:38:46 -0700 (PDT) Date: Mon, 02 Sep 2019 14:38:46 +0100 From: Rob Herring To: Henry Chen Cc: Georgi Djakov , Matthias Brugger , Viresh Kumar , Stephen Boyd , Ryan Case , Nicolas Boichat , Fan Chen , James Liao , Weiyi Lu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH V3 08/10] dt-bindings: interconnect: add MT8183 interconnect dt-bindings Message-ID: <20190902033045.GA10734@bogus> References: <1566995328-15158-1-git-send-email-henryc.chen@mediatek.com> <1566995328-15158-9-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1566995328-15158-9-git-send-email-henryc.chen@mediatek.com> X-Mutt-References: <1566995328-15158-9-git-send-email-henryc.chen@mediatek.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 28, 2019 at 08:28:46PM +0800, Henry Chen wrote: > Add interconnect provider dt-bindings for MT8183. > > Signed-off-by: Henry Chen > --- > .../devicetree/bindings/soc/mediatek/dvfsrc.txt | 9 +++++++++ > include/dt-bindings/interconnect/mtk,mt8183-emi.h | 18 ++++++++++++++++++ > 2 files changed, 27 insertions(+) > create mode 100644 include/dt-bindings/interconnect/mtk,mt8183-emi.h > > diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt > index 7f43499..da98ec9 100644 > --- a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt > +++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt > @@ -12,6 +12,11 @@ Required Properties: > - clock-names: Must include the following entries: > "dvfsrc": DVFSRC module clock > - clocks: Must contain an entry for each entry in clock-names. > +- #interconnect-cells : should contain 1 > +- interconnect : interconnect providers support dram bandwidth requirements. > + The provider is able to communicate with the DVFSRC and send the dram > + bandwidth to it. shall contain only one of the following: > + "mediatek,mt8183-emi" > > Example: > > @@ -20,4 +25,8 @@ Example: > reg = <0 0x10012000 0 0x1000>; > clocks = <&infracfg CLK_INFRA_DVFSRC>; > clock-names = "dvfsrc"; > + ddr_emi: interconnect { The EMI is a sub-module in the DVFSRC? This is the DDR controller or something else? > + compatible = "mediatek,mt8183-emi"; > + #interconnect-cells = <1>; > + }; > };