From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E520AC4CEC4 for ; Mon, 23 Sep 2019 18:27:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BBEC720665 for ; Mon, 23 Sep 2019 18:27:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1569263257; bh=lrTgo8gPdIMJ3llEv+oZl37eUQOe7SQwbk2ZMEq+Cpw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=Ub2n/kvDLJAmm2D3GxBbzFmXi44GqoFHuYNmSJMLCpFYxexNwZLm3egB+4cksw7Bq U48govEvPGJe9pxVZO/LA0yReU72PXxV/w7G+OMzMSx3cAvi/G+q+4aPAMztQ87e0J BVE7q3AWlC/7iNaQtQD4TcSwP/uOyzVABvw3zMGg= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2502374AbfIWS1h (ORCPT ); Mon, 23 Sep 2019 14:27:37 -0400 Received: from foss.arm.com ([217.140.110.172]:46970 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727731AbfIWS1f (ORCPT ); Mon, 23 Sep 2019 14:27:35 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 803781BB0; Mon, 23 Sep 2019 11:27:34 -0700 (PDT) Received: from big-swifty.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 845183F694; Mon, 23 Sep 2019 11:27:31 -0700 (PDT) From: Marc Zyngier To: kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org Cc: Eric Auger , James Morse , Julien Thierry , Suzuki K Poulose , Thomas Gleixner , Jason Cooper , Lorenzo Pieralisi , Andrew Murray Subject: [PATCH 18/35] irqchip/gic-v4.1: Add VPE INVALL callback Date: Mon, 23 Sep 2019 19:25:49 +0100 Message-Id: <20190923182606.32100-19-maz@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190923182606.32100-1-maz@kernel.org> References: <20190923182606.32100-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org GICv4.1 redistributors have a VPE-aware INVALL register. Progress! We can now emulate a guest-requested INVALL without emiting a VINVALL command. Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic-v3-its.c | 14 ++++++++++++++ include/linux/irqchip/arm-gic-v3.h | 3 +++ 2 files changed, 17 insertions(+) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 3079ce74def6..eda35e66237f 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -3506,6 +3506,19 @@ static void its_vpe_4_1_deschedule(struct its_vpe *vpe, } } +static void its_vpe_4_1_invall(struct its_vpe *vpe) +{ + void __iomem *rdbase; + u64 val; + + val = GICR_INVLPIR_V; + val |= FIELD_PREP(GICR_INVLPIR_VPEID, vpe->vpe_id); + + /* Target the redistributor this vPE is currently known on */ + rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; + gic_write_lpir(val, rdbase + GICR_INVALLR); +} + static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) { struct its_vpe *vpe = irq_data_get_irq_chip_data(d); @@ -3521,6 +3534,7 @@ static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) return 0; case INVALL_VPE: + its_vpe_4_1_invall(vpe); return 0; default: diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 6fd89d77b2b2..b69f60792554 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -247,6 +247,9 @@ #define GICR_TYPER_COMMON_LPI_AFF GENMASK_ULL(25, 24) #define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32) +#define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32) +#define GICR_INVLPIR_V GENMASK_ULL(63, 63) + #define GIC_V3_REDIST_SIZE 0x20000 #define LPI_PROP_GROUP1 (1 << 1) -- 2.20.1