From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 344C5C432C2 for ; Tue, 24 Sep 2019 16:57:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F35E121783 for ; Tue, 24 Sep 2019 16:57:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1569344271; bh=vNJVuAcZSGd4JfMJeT1HcCWqm+jXlfUf9xrhXZuLZQE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=ntb6OItr8Yoiozox5rTe7w1QcU3FvA822WeDakWGp3g1MQQnTJGiywQMIpIUACzuR 7tDYs9RV4kb9E5MNcXVE+xAjXRmzoK1A3THkmqsIODvrDKzwpcA0YGQ99iP1U2OI5M sQ9OTDVm/tfm0c9ZPvQGjpmagZUAE5n0u7t7h0b8= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393210AbfIXQsd (ORCPT ); Tue, 24 Sep 2019 12:48:33 -0400 Received: from mail.kernel.org ([198.145.29.99]:40194 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2633352AbfIXQsb (ORCPT ); Tue, 24 Sep 2019 12:48:31 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 18A0F20673; Tue, 24 Sep 2019 16:48:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1569343710; bh=vNJVuAcZSGd4JfMJeT1HcCWqm+jXlfUf9xrhXZuLZQE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gDt38CT6kPxXO9+AZZSifAGhBvD3CxMKHoE7wu9IGvaFswLdyqCUKl2DmuGTiwUnX mFxQBG7fP/HY0qYDPlUNgY6Oxy1Cob0G86rly1idOIxygdSlfl9pZLQ6BgAjbY7AF+ YN4KzHRN9Eg/7LCAWZtBYFAeAY+rsplCPEaudDFI= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Peng Fan , Leonard Crestez , Stephen Boyd , Sasha Levin , linux-clk@vger.kernel.org Subject: [PATCH AUTOSEL 5.2 61/70] clk: imx: clk-pll14xx: unbypass PLL by default Date: Tue, 24 Sep 2019 12:45:40 -0400 Message-Id: <20190924164549.27058-61-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190924164549.27058-1-sashal@kernel.org> References: <20190924164549.27058-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Peng Fan [ Upstream commit a9aa8306074d9519dd6e5fdf07240b01bac72e04 ] When registering the PLL, unbypass the PLL. The PLL has two bypass control bit, BYPASS and EXT_BYPASS. we will expose EXT_BYPASS to clk driver for mux usage, and keep BYPASS inside pll14xx usage. The PLL has a restriction that when M/P change, need to RESET/BYPASS pll to avoid glitch, so we could not expose BYPASS. To make it easy for clk driver usage, unbypass PLL which does not hurt current function. Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc") Reviewed-by: Leonard Crestez Signed-off-by: Peng Fan Link: https://lkml.kernel.org/r/1568043491-20680-3-git-send-email-peng.fan@nxp.com Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/imx/clk-pll14xx.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 656f48b002dd3..7a815ec76aa5c 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -368,6 +368,7 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, struct clk_pll14xx *pll; struct clk *clk; struct clk_init_data init; + u32 val; pll = kzalloc(sizeof(*pll), GFP_KERNEL); if (!pll) @@ -399,6 +400,10 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, pll->rate_table = pll_clk->rate_table; pll->rate_count = pll_clk->rate_count; + val = readl_relaxed(pll->base + GNRL_CTL); + val &= ~BYPASS_MASK; + writel_relaxed(val, pll->base + GNRL_CTL); + clk = clk_register(NULL, &pll->hw); if (IS_ERR(clk)) { pr_err("%s: failed to register pll %s %lu\n", -- 2.20.1