From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76A6AC432C2 for ; Wed, 25 Sep 2019 17:09:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 49DA52146E for ; Wed, 25 Sep 2019 17:09:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2392260AbfIYRJO (ORCPT ); Wed, 25 Sep 2019 13:09:14 -0400 Received: from foss.arm.com ([217.140.110.172]:55108 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731087AbfIYRJO (ORCPT ); Wed, 25 Sep 2019 13:09:14 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 849E11570; Wed, 25 Sep 2019 10:09:13 -0700 (PDT) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2A55C3F694; Wed, 25 Sep 2019 10:09:12 -0700 (PDT) Date: Wed, 25 Sep 2019 18:09:01 +0100 From: Andre Przywara To: Peng Fan Cc: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "jassisinghbrar@gmail.com" , "sudeep.holla@arm.com" , "f.fainelli@gmail.com" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , dl-linux-imx Subject: Re: [PATCH V9 1/2] dt-bindings: mailbox: add binding doc for the ARM SMC/HVC mailbox Message-ID: <20190925180901.11fe5165@donnerap.cambridge.arm.com> In-Reply-To: <1569377224-5755-2-git-send-email-peng.fan@nxp.com> References: <1569377224-5755-1-git-send-email-peng.fan@nxp.com> <1569377224-5755-2-git-send-email-peng.fan@nxp.com> Organization: ARM X-Mailer: Claws Mail 3.17.3 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 25 Sep 2019 02:09:08 +0000 Peng Fan wrote: Hi, > From: Peng Fan > > The ARM SMC/HVC mailbox binding describes a firmware interface to trigger > actions in software layers running in the EL2 or EL3 exception levels. > The term "ARM" here relates to the SMC instruction as part of the ARM > instruction set, not as a standard endorsed by ARM Ltd. > > Signed-off-by: Peng Fan > Reviewed-by: Florian Fainelli > --- > .../devicetree/bindings/mailbox/arm-smc.yaml | 96 ++++++++++++++++++++++ > 1 file changed, 96 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mailbox/arm-smc.yaml > > diff --git a/Documentation/devicetree/bindings/mailbox/arm-smc.yaml b/Documentation/devicetree/bindings/mailbox/arm-smc.yaml > new file mode 100644 > index 000000000000..b061954d1678 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mailbox/arm-smc.yaml > @@ -0,0 +1,96 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mailbox/arm-smc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ARM SMC Mailbox Interface > + > +maintainers: > + - Peng Fan > + > +description: | > + This mailbox uses the ARM smc (secure monitor call) or hvc (hypervisor > + call) instruction to trigger a mailbox-connected activity in firmware, > + executing on the very same core as the caller. The value of r0/w0/x0 > + the firmware returns after the smc call is delivered as a received > + message to the mailbox framework, so synchronous communication can be > + established. The exact meaning of the action the mailbox triggers as > + well as the return value is defined by their users and is not subject > + to this binding. > + > + One example use case of this mailbox is the SCMI interface, which uses > + shared memory to transfer commands and parameters, and a mailbox to > + trigger a function call. This allows SoCs without a separate management > + processor (or when such a processor is not available or used) to use > + this standardized interface anyway. > + > + This binding describes no hardware, but establishes a firmware interface. > + Upon receiving an SMC using the described SMC function identifier, the > + firmware is expected to trigger some mailbox connected functionality. > + The communication follows the ARM SMC calling convention. > + Firmware expects an SMC function identifier in r0 or w0. The supported > + identifier are passed from consumers, or listed in the the arm,func-id ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This is now obsolete. The rest looks good to me, thanks for the changes! Reviewed-by: Andre Przywara Cheers, Andre. > + property as described below. The firmware can return one value in > + the first SMC result register, it is expected to be an error value, > + which shall be propagated to the mailbox client. > + > + Any core which supports the SMC or HVC instruction can be used, as long > + as a firmware component running in EL3 or EL2 is handling these calls. > + > +properties: > + compatible: > + oneOf: > + - description: > + For implementations using ARM SMC instruction. > + const: arm,smc-mbox > + > + - description: > + For implementations using ARM HVC instruction. > + const: arm,hvc-mbox > + > + "#mbox-cells": > + const: 0 > + > + arm,func-id: > + description: | > + An single 32-bit value specifying the function ID used by the mailbox. > + The function ID follows the ARM SMC calling convention standard. > + $ref: /schemas/types.yaml#/definitions/uint32 > + > +required: > + - compatible > + - "#mbox-cells" > + - arm,func-id > + > +examples: > + - | > + sram@93f000 { > + compatible = "mmio-sram"; > + reg = <0x0 0x93f000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x93f000 0x1000>; > + > + cpu_scp_lpri: scp-shmem@0 { > + compatible = "arm,scmi-shmem"; > + reg = <0x0 0x200>; > + }; > + }; > + > + smc_tx_mbox: tx_mbox { > + #mbox-cells = <0>; > + compatible = "arm,smc-mbox"; > + arm,func-id = <0xc20000fe>; > + }; > + > + firmware { > + scmi { > + compatible = "arm,scmi"; > + mboxes = <&smc_tx_mbox>; > + mbox-names = "tx"; > + shmem = <&cpu_scp_lpri>; > + }; > + }; > + > +...