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[85.30.9.151]) by smtp.gmail.com with ESMTPSA id p3sm2520051ljn.78.2019.09.29.11.22.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 29 Sep 2019 11:22:22 -0700 (PDT) Date: Sun, 29 Sep 2019 10:51:34 -0700 From: Olof Johansson To: Krzysztof Kozlowski Cc: Arnd Bergmann , arm-soc , SoC Team , Kukjin Kim , Linux ARM , "moderated list:ARM/SAMSUNG EXYNOS ARM ARCHITECTURES" , "linux-kernel@vger.kernel.org" , DTML Subject: Re: [GIT PULL 1/2] arm64: dts: exynos: Pull for v5.4 Message-ID: <20190929175134.fsieffurfdiqhpj2@localhost> References: <20190911183632.4317-1-krzk@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Thu, Sep 12, 2019 at 08:32:47AM +0200, Krzysztof Kozlowski wrote: > On Wed, 11 Sep 2019 at 23:07, Arnd Bergmann wrote: > > > > On Wed, Sep 11, 2019 at 8:36 PM Krzysztof Kozlowski wrote: > > > > > > Hi, > > > > > > Unfortunately the patches were applied right after closing the linux-next. > > > > Hi Krzysztof, > > > > I took a look at these and am not convinced this is right: > > > > > 1. Fix boot of Exynos7 due to wrong address/size of memory node, > > > > The current state is clearly broken and a fix is needed, but > > I'm not sure this is the right fix. Why do you have 32-bit physical > > addressing on a 64-bit chip? I looked at commit ef72171b3621 > > that introduced it, and it seems it would be better to just > > revert back to 64-bit addresses. > > We discussed with Marek Szyprowski that either we can go back to > 64-bit addressing or stick to 32. There are not known boards with more > than 4 GB of RAM so from this point of view the choice was irrelevant. > At the end of discussion I mentioned to stick with other arm64 boards > (although not all), so revert to have 64 bit address... but Marek > chosen differently. Since you ask, let's go back with revert. > > > > > > 2. Move GPU under /soc node, > > > > No problem > > > > > 3. Minor cleanup of #address-cells. > > > > IIRC, an interrupt-controller is required to have a #address-cells > > property, even if that is normally zero. I don't remember the > > details, but the gic binding lists it as mandatory, and I think > > the PCI interrupt-map relies on it. I would just drop this patch. > > Indeed, binding requires both address and size cells. I'll drop it. Looking through the history of pending material, I didn't see a new pull for this material. Just checking in to see if there's something we missed? Thanks, -Olof