From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0A77C352AA for ; Tue, 1 Oct 2019 17:02:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 84FB92054F for ; Tue, 1 Oct 2019 17:02:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1569949344; bh=QW0ekt2NVtSUYBkmf2MI5jiIISU16b48NI9jA7OHoJY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=APhowBUl7k+fbycvnzo64advqmDl32IDBmq2peE86pu4wVyWuN5IQLkaWSX0vBGtw y7B+OaP8/hby4OkQuuSViGX1zbCdCNgZTSNEq4b07POWhOIdB23Z7Xe6ql3/8ECy1/ hsey13Qm8crSDR4nQEXaBtQFZVoU2A/k6BlO56ac= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729537AbfJAQkF (ORCPT ); Tue, 1 Oct 2019 12:40:05 -0400 Received: from mail.kernel.org ([198.145.29.99]:51154 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729254AbfJAQkA (ORCPT ); Tue, 1 Oct 2019 12:40:00 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id CC1C02190F; Tue, 1 Oct 2019 16:39:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1569947999; bh=QW0ekt2NVtSUYBkmf2MI5jiIISU16b48NI9jA7OHoJY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U2sxihZ/5ESRDgKQL7TyJM01KgJ0AE2WlLCEe8i6pahu//PjPfNuSJqGG8BnGkvwZ 3XPb47IN6FxqkDXU9bQK3EJ00E4Jh/WwKepzn8WictLE8a1nRosLCU5Rt/1KFDfqRF 3IJ2ve+U8na9xX/AQr4DyXzVx+Ftwk6F1yoTUgIk= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Fabrice Gasnier , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Thierry Reding , Sasha Levin , linux-pwm@vger.kernel.org Subject: [PATCH AUTOSEL 5.3 25/71] pwm: stm32-lp: Add check in case requested period cannot be achieved Date: Tue, 1 Oct 2019 12:38:35 -0400 Message-Id: <20191001163922.14735-25-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191001163922.14735-1-sashal@kernel.org> References: <20191001163922.14735-1-sashal@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabrice Gasnier [ Upstream commit c91e3234c6035baf5a79763cb4fcd5d23ce75c2b ] LPTimer can use a 32KHz clock for counting. It depends on clock tree configuration. In such a case, PWM output frequency range is limited. Although unlikely, nothing prevents user from requesting a PWM frequency above counting clock (32KHz for instance): - This causes (prd - 1) = 0xffff to be written in ARR register later in the apply() routine. This results in badly configured PWM period (and also duty_cycle). Add a check to report an error is such a case. Signed-off-by: Fabrice Gasnier Reviewed-by: Uwe Kleine-König Signed-off-by: Thierry Reding Signed-off-by: Sasha Levin --- drivers/pwm/pwm-stm32-lp.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pwm/pwm-stm32-lp.c b/drivers/pwm/pwm-stm32-lp.c index 2211a642066db..97a9afa191ee0 100644 --- a/drivers/pwm/pwm-stm32-lp.c +++ b/drivers/pwm/pwm-stm32-lp.c @@ -59,6 +59,12 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm, /* Calculate the period and prescaler value */ div = (unsigned long long)clk_get_rate(priv->clk) * state->period; do_div(div, NSEC_PER_SEC); + if (!div) { + /* Clock is too slow to achieve requested period. */ + dev_dbg(priv->chip.dev, "Can't reach %u ns\n", state->period); + return -EINVAL; + } + prd = div; while (div > STM32_LPTIM_MAX_ARR) { presc++; -- 2.20.1