From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AEFAECE58E for ; Mon, 7 Oct 2019 17:10:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5C53F206C0 for ; Mon, 7 Oct 2019 17:10:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729187AbfJGRKP (ORCPT ); Mon, 7 Oct 2019 13:10:15 -0400 Received: from mga01.intel.com ([192.55.52.88]:15254 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728048AbfJGRKO (ORCPT ); Mon, 7 Oct 2019 13:10:14 -0400 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 10:10:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,268,1566889200"; d="scan'208";a="368177334" Received: from sjchrist-coffee.jf.intel.com (HELO linux.intel.com) ([10.54.74.41]) by orsmga005.jf.intel.com with ESMTP; 07 Oct 2019 10:10:13 -0700 Date: Mon, 7 Oct 2019 10:10:13 -0700 From: Sean Christopherson To: Paolo Bonzini Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, Peter Zijlstra , Arnaldo Carvalho de Melo , Radim =?utf-8?B?S3LEjW3DocWZ?= , Tony Luck , Tony W Wang-oc , "H. Peter Anvin" , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-edac@vger.kernel.org, Borislav Petkov , Jarkko Sakkinen Subject: Re: [PATCH 01/16] x86/intel: Initialize IA32_FEATURE_CONTROL MSR at boot Message-ID: <20191007171013.GD18016@linux.intel.com> References: <20191004215615.5479-1-sean.j.christopherson@intel.com> <20191004215615.5479-2-sean.j.christopherson@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 07, 2019 at 07:05:32PM +0200, Paolo Bonzini wrote: > On 04/10/19 23:56, Sean Christopherson wrote: > > Always lock IA32_FEATURE_CONTROL if it exists, even if the CPU doesn't > > support VMX, so that other existing and future kernel code that queries > > IA32_FEATURE_CONTROL can assume it's locked. > > Possibly stupid question: why bother locking it? It makes sense to lock > the MSR bits to _off_ in the firmware, but if the BIOS hasn't locked it, > why should the OS? > > It seems to me that locking introduces a lot of complication. None of the enable bits take effect until the MSR is locked. If I had to guess, ucode likely goes and pokes the enabled features during the WRMSR with the lock bit set, as opposed to the relevant features querying the MSR value as needed (querying the MSR is likely slow).