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Mon, 7 Oct 2019 23:39:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1570491546; bh=pHvuvtluuEtoXPJ6Nnr1FZAfPESLSfIJNq3Czhj/Tf0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=EkvVh0rV3EOnNjWHRYMlU5CKZy+jEwzajJnDFeq1Wy1Lvy+Sc9EqofQf1mlt41XTn 1U/Qx61m2O4QGVq3i0nXF+s3f4zRd2PfklU/1LTfuNxYrmd8Xl/XIj/1ArKXu6z+Iz 6iYD1+JRqWey4KK3yrExKcOsC3pz0Vnjwrmx/9TY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org BB48D602D8 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jackp@codeaurora.org Date: Mon, 7 Oct 2019 16:39:04 -0700 From: Jack Pham To: John Stultz , Yu Chen , Felipe Balbi Cc: lkml , Greg Kroah-Hartman , Andy Shevchenko , Rob Herring , Mark Rutland , Matthias Brugger , Chunfeng Yun , linux-usb@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [RFC][PATCH v2 2/5] usb: dwc3: Execute GCTL Core Soft Reset while switch mdoe for Hisilicon Kirin Soc Message-ID: <20191007233904.GC9754@jackp-linux.qualcomm.com> References: <20191007175553.66940-1-john.stultz@linaro.org> <20191007175553.66940-3-john.stultz@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191007175553.66940-3-john.stultz@linaro.org> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi John, Yu, Felipe, On Mon, Oct 07, 2019 at 05:55:50PM +0000, John Stultz wrote: > From: Yu Chen > > A GCTL soft reset should be executed when switch mode for dwc3 core > of Hisilicon Kirin Soc. > > Cc: Greg Kroah-Hartman > Cc: Felipe Balbi > Cc: Andy Shevchenko > Cc: Rob Herring > Cc: Mark Rutland > Cc: Yu Chen > Cc: Matthias Brugger > Cc: Chunfeng Yun > Cc: linux-usb@vger.kernel.org > Cc: devicetree@vger.kernel.org > Signed-off-by: Yu Chen > Signed-off-by: John Stultz > --- > drivers/usb/dwc3/core.c | 20 ++++++++++++++++++++ > drivers/usb/dwc3/core.h | 3 +++ > 2 files changed, 23 insertions(+) > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c > index 999ce5e84d3c..440261432421 100644 > --- a/drivers/usb/dwc3/core.c > +++ b/drivers/usb/dwc3/core.c > @@ -112,6 +112,19 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) > dwc->current_dr_role = mode; > } > > +static void dwc3_gctl_core_soft_reset(struct dwc3 *dwc) > +{ > + u32 reg; > + > + reg = dwc3_readl(dwc->regs, DWC3_GCTL); > + reg |= DWC3_GCTL_CORESOFTRESET; > + dwc3_writel(dwc->regs, DWC3_GCTL, reg); > + > + reg = dwc3_readl(dwc->regs, DWC3_GCTL); > + reg &= ~DWC3_GCTL_CORESOFTRESET; > + dwc3_writel(dwc->regs, DWC3_GCTL, reg); > +} > + > static void __dwc3_set_mode(struct work_struct *work) > { > struct dwc3 *dwc = work_to_dwc(work); > @@ -156,6 +169,10 @@ static void __dwc3_set_mode(struct work_struct *work) > > dwc3_set_prtcap(dwc, dwc->desired_dr_role); > > + /* Execute a GCTL Core Soft Reset when switch mode */ > + if (dwc->gctl_reset_quirk) > + dwc3_gctl_core_soft_reset(dwc); > + In fact it is mentioned in the Synopsys databook to perform a GCTL CoreSoftReset when changing the PrtCapDir between device & host modes. So I think this should apply generally without a quirk. Further, it states to do this *prior* to writing PrtCapDir, so should it go before dwc3_set_prtcap() instead? Jack -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project