From: Catalin Marinas <catalin.marinas@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
James Morse <james.morse@arm.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
huawei.libin@huawei.com, uohanjun@huawei.com,
liwei391@huawei.com, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 0/2] arm64: Relax ICC_PMR_EL1 synchronisation when possible
Date: Tue, 15 Oct 2019 18:30:36 +0100 [thread overview]
Message-ID: <20191015173035.GN13874@arrakis.emea.arm.com> (raw)
In-Reply-To: <20191002090613.14236-1-maz@kernel.org>
On Wed, Oct 02, 2019 at 10:06:11AM +0100, Marc Zyngier wrote:
> This is a very late update on [1], fixing the 32bit compilation issue that
> was present in v2, and adding an extra message in the kernel log to find out
> what is going on.
>
> [1] http://lore.kernel.org/r/20190802125208.73162-1-maz@kernel.org
>
> Marc Zyngier (2):
> arm64: Relax ICC_PMR_EL1 accesses when ICC_CTLR_EL1.PMHE is clear
> arm64: Document ICC_CTLR_EL3.PMHE setting requirements
Queued for 5.5. Thanks.
--
Catalin
prev parent reply other threads:[~2019-10-15 17:30 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-02 9:06 [PATCH v3 0/2] arm64: Relax ICC_PMR_EL1 synchronisation when possible Marc Zyngier
2019-10-02 9:06 ` [PATCH v3 1/2] arm64: Relax ICC_PMR_EL1 accesses when ICC_CTLR_EL1.PMHE is clear Marc Zyngier
2019-10-23 8:38 ` liwei (GF)
2019-10-23 12:13 ` Marc Zyngier
2019-10-26 1:42 ` liwei (GF)
2019-10-02 9:06 ` [PATCH v3 2/2] arm64: Document ICC_CTLR_EL3.PMHE setting requirements Marc Zyngier
2019-10-15 17:30 ` Catalin Marinas [this message]
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