From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8136CCA9EA0 for ; Fri, 18 Oct 2019 15:46:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 56295222C6 for ; Fri, 18 Oct 2019 15:46:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="oRj+0dNd" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405669AbfJRPqr (ORCPT ); Fri, 18 Oct 2019 11:46:47 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:49666 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2502233AbfJRPqV (ORCPT ); Fri, 18 Oct 2019 11:46:21 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFkIgX016653; Fri, 18 Oct 2019 10:46:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571413578; bh=v8OG3LksgH1i+Pb5OuMPKQYp8bn+sVIBG+lclhVp8Ag=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=oRj+0dNdqZgFmbLZhvNNHUKddMju3pnW3pBFLrybjkzLw/NgkDDOYclecIhJSHLbN c10HfEpR2efGYm2oub5UqCM6wTSY0oqMUodOANILSwXszzDDiqq2QGoleRiLaBSTbN OlfY9xNDd5Gc8SOZMNQXytQQPTLho2TFiaI3/WAY= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9IFkIJP109094 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Oct 2019 10:46:18 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:46:10 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:46:10 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFkDAQ045642; Fri, 18 Oct 2019 10:46:18 -0500 From: Benoit Parrot To: Tony Lindgren , Tero Kristo CC: Rob Herring , , , , Benoit Parrot Subject: [Patch 4/9] ARM: dts: DRA72: Add CAL dtsi node Date: Fri, 18 Oct 2019 10:48:44 -0500 Message-ID: <20191018154849.3127-5-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018154849.3127-1-bparrot@ti.com> References: <20191018154849.3127-1-bparrot@ti.com> MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds the required dtsi node to support the Camera Adaptation Layer (CAL) for the DRA72 family of devices. Signed-off-by: Benoit Parrot --- arch/arm/boot/dts/dra72x.dtsi | 43 +++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi index f5762709c853..29d4c7664e90 100644 --- a/arch/arm/boot/dts/dra72x.dtsi +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -17,6 +17,49 @@ }; }; +&l4_per2 { + target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5b000 0x4>, + <0x5b010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + ; + ti,sysc-sidle = , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + + cal: cal@0 { + compatible = "ti,dra72-cal"; + reg = <0x0000 0x400>, + <0x0800 0x40>, + <0x0900 0x40>; + reg-names = "cal_top", + "cal_rx_core0", + "cal_rx_core1"; + interrupts = ; + syscon-camerrx = <&scm_conf 0xE94>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_0: port@0 { + reg = <0>; + }; + csi2_1: port@1 { + reg = <1>; + }; + }; + }; + }; +}; + &dss { reg = <0x58000000 0x80>, <0x58004054 0x4>, -- 2.17.1