Re: [PATCH 06/12] riscv: add support for MMIO access to the timer registers

Thomas Gleixner
2019-11-12T10:39:16Z

On Mon, 28 Oct 2019, Christoph Hellwig wrote:

> When running in M-mode we can't use the SBI to set the timer, and
> don't have access to the time CSR as that usually is emulated by
> M-mode. Instead provide code that directly accesses the MMIO for
> the timer.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> arch/riscv/include/asm/sbi.h | 3 ++-
> arch/riscv/include/asm/timex.h | 19 +++++++++++++++++--
> drivers/clocksource/timer-riscv.c | 21 +++++++++++++++++----

Acked-by: Thomas Gleixner <tglx@linutronix.de>