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Mon, 11 Nov 2019 03:17:27 -0500 Received: by mail-wr1-f68.google.com with SMTP id i10so13529734wrs.7 for ; Mon, 11 Nov 2019 00:17:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=VsDEMrW/RrcxhRY1vm2HEmbhOBjQCGmnH7miF+ASOOE=; b=dcluWyIwC0AdhNW+RROY3tTV7NkIFLNALJW6YRUeoVaa82SQwt80DfSxG1hGtkz2pq VELwGauGVA+xgVx0MK+yrpkr65Bsw8gfIgFPGpg1Qe4V/boROsLDw5WjHU7IZNpjt39B zGtNnDZ6Il+huxIOnoaJqLX7un8nvqDdqrwy+Y7LJUENYR6O8crz7HtuhJpfN61/AzgZ 8fKYF4TVSk+fnXFT4lBf8vdGMlCT1w5UUE2+WMqs0TYdJYvK8gSxYJU8BGZDtuRoIrSw Tso2FqKD1HWi/+RUWE7FY7PVocvZKmfMYdJcHYDaVMkqsCjmtpfY7v0A4uzZG0z/tjxa 42rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=VsDEMrW/RrcxhRY1vm2HEmbhOBjQCGmnH7miF+ASOOE=; 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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20191026214732.17725-1-linus.walleij@linaro.org> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 26 Oct 2019, Linus Walleij wrote: > There is a distinct version of the Ux500 U8420 variant > with "sysclk", as can be seen from the vendor code that > didn't make it upstream, this firmware lacks the > ULPPLL (ultra-low power phase locked loop) which in > effect means that the timer clock is instead wired to > the 32768 Hz always-on clock. > > This has some repercussions when enabling the timer > clock as the code as it stands will disable the timer > clock on these platforms (lacking the so-called > "doze mode") and obtaining the wrong rate of the timer > clock. > > The timer frequency is of course needed very early in > the boot, and as a consequence, we need to shuffle > around the early PRCMU init code: whereas in the past > we did not need to look up the PRCMU firmware version > in the early init, but now we need to know the version > before the core system timers are registered so we > restructure the platform callbacks to the PRCMU so as > not to take any arguments and instead look up the > resources it needs directly from the device tree > when initializing. > > As we do not yet support any platforms using this > firmware it is not a regression, but as PostmarketOS > is starting to support products with this firmware we > need to fix this up. > > The low rate of 32kHz also makes the MTU timer unsuitable > as delay timer but this needs to be fixed in a separate > patch. > > Cc: arm@kernel.org > Cc: Lee Jones > Cc: Stephan Gerhold > Signed-off-by: Linus Walleij > --- > ChangeLog v2->v3: > - It's a bad idead to return -ENODEV in a function > that returns void. > ChangeLog v1->v2: > - Change the style of the ULPPLL check function (more > compact) > - Fix a missing of_node_put() by actually returning > with -ENODEV on error. > > ARM SoC folks: as this mostly affects the MFD subsystems > I think it'd be best if Lee can merge it, I do not > plan any other changes to the ARM core files that the > patch touches. > --- > arch/arm/mach-ux500/cpu-db8500.c | 2 +- > drivers/mfd/db8500-prcmu.c | 63 ++++++++++++++++++++++---------- > include/linux/mfd/db8500-prcmu.h | 4 +- > include/linux/mfd/dbx500-prcmu.h | 7 ++-- > 4 files changed, 50 insertions(+), 26 deletions(-) Applied, thanks. -- Lee Jones [李琼斯] Linaro Services Technical Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog