From: Peter Zijlstra <peterz@infradead.org>
To: kan.liang@linux.intel.com
Cc: acme@redhat.com, mingo@kernel.org, linux-kernel@vger.kernel.org,
ak@linux.intel.com, eranian@google.com
Subject: Re: [PATCH] perf/x86/intel: Avoid PEBS_ENABLE MSR access in PMI
Date: Fri, 15 Nov 2019 15:07:39 +0100 [thread overview]
Message-ID: <20191115140739.GM4131@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20191115133917.24424-1-kan.liang@linux.intel.com>
On Fri, Nov 15, 2019 at 05:39:17AM -0800, kan.liang@linux.intel.com wrote:
> From: Kan Liang <kan.liang@linux.intel.com>
>
> The perf PMI handler, intel_pmu_handle_irq(), currently does
> unnecessary MSR accesses when PEBS is enabled.
>
> When entering the handler, global ctrl is explicitly disabled. All
> counters do not count anymore. It doesn't matter if the PEBS is
> enabled or disabled. Furthermore, cpuc->pebs_enabled is not changed
> in PMI. The PEBS status doesn't change. The PEBS_ENABLE MSR doesn't need
> to be changed either.
PMI can throttle, and iirc x86_pmu_stop() ends up in
intel_pmu_pebs_disable()
next prev parent reply other threads:[~2019-11-15 14:07 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-15 13:39 [PATCH] perf/x86/intel: Avoid PEBS_ENABLE MSR access in PMI kan.liang
2019-11-15 14:07 ` Peter Zijlstra [this message]
2019-11-15 14:46 ` Liang, Kan
2019-11-15 18:04 ` Liang, Kan
2019-11-15 18:33 ` Andi Kleen
2019-11-15 18:42 ` Liang, Kan
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