From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=DKIMWL_WL_MED,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT, USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB6C7C432C3 for ; Fri, 15 Nov 2019 19:17:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9440D20733 for ; Fri, 15 Nov 2019 19:17:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="hfj3euSo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726809AbfKOTRp (ORCPT ); Fri, 15 Nov 2019 14:17:45 -0500 Received: from mail-wr1-f73.google.com ([209.85.221.73]:34329 "EHLO mail-wr1-f73.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726075AbfKOTRo (ORCPT ); Fri, 15 Nov 2019 14:17:44 -0500 Received: by mail-wr1-f73.google.com with SMTP id c16so8405706wro.1 for ; Fri, 15 Nov 2019 11:17:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:message-id:mime-version:subject:from:to:cc; bh=sOSahxtVzmMy//+sngzoRwO73Kt/9r0KRyyDuBPBx88=; b=hfj3euSobTPiS1fboAdGh8Ujy80sHN9Qc0X04dz2giNU8PRrXlUSqdX0Qd0jG+GJBP 3hbqYaSkWmOBK9C4zpWXbKe4JHkv1YYqyMyWG9VqPdX3xkilbwlIXmf0/bQv+JXtaUMY pcITIkF8dB7v+gBdafBI6yjPxRik+INoMFptMCVM4BtWiSgg9a/SfaAVwxUXIDur2Dky lGSLQ4Ka1Wiw8bR3I93pwxEf1Gnf6QgokZxyMJELHsF6hWyA5d3/GPvqLPNMvyVd9JQ3 LstI0rvPYmNOZvTwa8R71hD/RmzPkVXlYgOF/PXDlP/zl8SdkKmFaJD6huCD4G6u/w2z JLkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; bh=sOSahxtVzmMy//+sngzoRwO73Kt/9r0KRyyDuBPBx88=; b=UrLLa7mdtDPiXesCZ7MKnHLExLFktl3CF0EcGCdNqeIcpO46ub/gMrlsv8fMMEO9ZT NNJAaozqvkTGWTgd2+RnD03aq5BrNLaFiS/qPtRv+MVdp/Pl23v8rZYI2DN7Fh2xuPvk 3jwD9/9qHjWsqKD/YHAEzeUfTH+3xdjHdLHx+Am3v8GGoiwcYgk4+OkOTTlisZ7zusgh zKVLLuLmhv9R0rLaUCr2FoDkn/U8jpO9XvhK+pD1qNGWYIAsRWeK1pFqozL6xQpzVK8H ihxazAGpm5Yq9RqtRRUCAyYEqgYLfMce4K9JXfegEZPAdxGZHWw/vKXwpmclkPRAsNS9 mRPQ== X-Gm-Message-State: APjAAAUnEAWzp8iVWlAj/XZqHUUomHxQvrunsCAmmlqEni1bkbOtQI/G XMg51juuHrpw9xVIkDb5B7rmrftJ2A== X-Google-Smtp-Source: APXvYqxPaXAY1MR3yo4tnAa0Wmn+pBadrdnhb2Lt+QaNX7WNZCb0GNIrG2rBRjA2K1n0g8S6YZa8HhUQhA== X-Received: by 2002:a5d:50c3:: with SMTP id f3mr4836854wrt.14.1573845459506; Fri, 15 Nov 2019 11:17:39 -0800 (PST) Date: Fri, 15 Nov 2019 20:17:26 +0100 Message-Id: <20191115191728.87338-1-jannh@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog Subject: [PATCH v2 1/3] x86/insn-eval: Add support for 64-bit kernel mode From: Jann Horn To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , x86@kernel.org, Andrey Ryabinin , Alexander Potapenko , Dmitry Vyukov , kasan-dev@googlegroups.com, jannh@google.com Cc: linux-kernel@vger.kernel.org, Andrey Konovalov , Andy Lutomirski , Sean Christopherson Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To support evaluating 64-bit kernel mode instructions: Replace existing checks for user_64bit_mode() with a new helper that checks whether code is being executed in either 64-bit kernel mode or 64-bit user mode. Select the GS base depending on whether the instruction is being evaluated in kernel mode. Signed-off-by: Jann Horn --- Notes: v2: no changes arch/x86/include/asm/ptrace.h | 13 +++++++++++++ arch/x86/lib/insn-eval.c | 26 +++++++++++++++----------- 2 files changed, 28 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h index 5057a8ed100b..ac45b06941a5 100644 --- a/arch/x86/include/asm/ptrace.h +++ b/arch/x86/include/asm/ptrace.h @@ -159,6 +159,19 @@ static inline bool user_64bit_mode(struct pt_regs *regs) #endif } +/* + * Determine whether the register set came from any context that is running in + * 64-bit mode. + */ +static inline bool any_64bit_mode(struct pt_regs *regs) +{ +#ifdef CONFIG_X86_64 + return !user_mode(regs) || user_64bit_mode(regs); +#else + return false; +#endif +} + #ifdef CONFIG_X86_64 #define current_user_stack_pointer() current_pt_regs()->sp #define compat_user_stack_pointer() current_pt_regs()->sp diff --git a/arch/x86/lib/insn-eval.c b/arch/x86/lib/insn-eval.c index 306c3a0902ba..31600d851fd8 100644 --- a/arch/x86/lib/insn-eval.c +++ b/arch/x86/lib/insn-eval.c @@ -155,7 +155,7 @@ static bool check_seg_overrides(struct insn *insn, int regoff) */ static int resolve_default_seg(struct insn *insn, struct pt_regs *regs, int off) { - if (user_64bit_mode(regs)) + if (any_64bit_mode(regs)) return INAT_SEG_REG_IGNORE; /* * Resolve the default segment register as described in Section 3.7.4 @@ -266,7 +266,7 @@ static int resolve_seg_reg(struct insn *insn, struct pt_regs *regs, int regoff) * which may be invalid at this point. */ if (regoff == offsetof(struct pt_regs, ip)) { - if (user_64bit_mode(regs)) + if (any_64bit_mode(regs)) return INAT_SEG_REG_IGNORE; else return INAT_SEG_REG_CS; @@ -289,7 +289,7 @@ static int resolve_seg_reg(struct insn *insn, struct pt_regs *regs, int regoff) * In long mode, segment override prefixes are ignored, except for * overrides for FS and GS. */ - if (user_64bit_mode(regs)) { + if (any_64bit_mode(regs)) { if (idx != INAT_SEG_REG_FS && idx != INAT_SEG_REG_GS) idx = INAT_SEG_REG_IGNORE; @@ -646,23 +646,27 @@ unsigned long insn_get_seg_base(struct pt_regs *regs, int seg_reg_idx) */ return (unsigned long)(sel << 4); - if (user_64bit_mode(regs)) { + if (any_64bit_mode(regs)) { /* * Only FS or GS will have a base address, the rest of * the segments' bases are forced to 0. */ unsigned long base; - if (seg_reg_idx == INAT_SEG_REG_FS) + if (seg_reg_idx == INAT_SEG_REG_FS) { rdmsrl(MSR_FS_BASE, base); - else if (seg_reg_idx == INAT_SEG_REG_GS) + } else if (seg_reg_idx == INAT_SEG_REG_GS) { /* * swapgs was called at the kernel entry point. Thus, * MSR_KERNEL_GS_BASE will have the user-space GS base. */ - rdmsrl(MSR_KERNEL_GS_BASE, base); - else + if (user_mode(regs)) + rdmsrl(MSR_KERNEL_GS_BASE, base); + else + rdmsrl(MSR_GS_BASE, base); + } else { base = 0; + } return base; } @@ -703,7 +707,7 @@ static unsigned long get_seg_limit(struct pt_regs *regs, int seg_reg_idx) if (sel < 0) return 0; - if (user_64bit_mode(regs) || v8086_mode(regs)) + if (any_64bit_mode(regs) || v8086_mode(regs)) return -1L; if (!sel) @@ -948,7 +952,7 @@ static int get_eff_addr_modrm(struct insn *insn, struct pt_regs *regs, * following instruction. */ if (*regoff == -EDOM) { - if (user_64bit_mode(regs)) + if (any_64bit_mode(regs)) tmp = regs->ip + insn->length; else tmp = 0; @@ -1250,7 +1254,7 @@ static void __user *get_addr_ref_32(struct insn *insn, struct pt_regs *regs) * After computed, the effective address is treated as an unsigned * quantity. */ - if (!user_64bit_mode(regs) && ((unsigned int)eff_addr > seg_limit)) + if (!any_64bit_mode(regs) && ((unsigned int)eff_addr > seg_limit)) goto out; /* -- 2.24.0.432.g9d3f5f5b63-goog