From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89513C432C0 for ; Thu, 28 Nov 2019 02:30:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 699802158A for ; Thu, 28 Nov 2019 02:30:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728312AbfK1CaG (ORCPT ); Wed, 27 Nov 2019 21:30:06 -0500 Received: from mga18.intel.com ([134.134.136.126]:17935 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728290AbfK1CaE (ORCPT ); Wed, 27 Nov 2019 21:30:04 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Nov 2019 18:30:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,251,1571727600"; d="scan'208";a="221176157" Received: from allen-box.sh.intel.com ([10.239.159.136]) by orsmga002.jf.intel.com with ESMTP; 27 Nov 2019 18:30:01 -0800 From: Lu Baolu To: Joerg Roedel , David Woodhouse , Alex Williamson Cc: ashok.raj@intel.com, sanjay.k.kumar@intel.com, jacob.jun.pan@linux.intel.com, kevin.tian@intel.com, yi.l.liu@intel.com, yi.y.sun@intel.com, Peter Xu , iommu@lists.linux-foundation.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Lu Baolu , Yi Sun Subject: [PATCH v2 3/8] iommu/vt-d: Implement second level page table ops Date: Thu, 28 Nov 2019 10:25:45 +0800 Message-Id: <20191128022550.9832-4-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191128022550.9832-1-baolu.lu@linux.intel.com> References: <20191128022550.9832-1-baolu.lu@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds the implementation of page table callbacks for the second level page table. Cc: Ashok Raj Cc: Jacob Pan Cc: Kevin Tian Cc: Liu Yi L Cc: Yi Sun Signed-off-by: Lu Baolu --- drivers/iommu/intel-iommu.c | 81 +++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c index 7752ff299cb5..96ead4e3395a 100644 --- a/drivers/iommu/intel-iommu.c +++ b/drivers/iommu/intel-iommu.c @@ -413,6 +413,7 @@ int for_each_device_domain(int (*fn)(struct device_domain_info *info, } const struct iommu_ops intel_iommu_ops; +static const struct pgtable_ops second_lvl_pgtable_ops; static bool translation_pre_enabled(struct intel_iommu *iommu) { @@ -1720,6 +1721,7 @@ static struct dmar_domain *alloc_domain(int flags) domain->nid = NUMA_NO_NODE; domain->flags = flags; domain->has_iotlb_device = false; + domain->ops = &second_lvl_pgtable_ops; INIT_LIST_HEAD(&domain->devices); return domain; @@ -2334,6 +2336,85 @@ static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, return 0; } +static int second_lvl_domain_map_range(struct dmar_domain *domain, + unsigned long iova, phys_addr_t paddr, + size_t size, int prot) +{ + return __domain_mapping(domain, iova >> VTD_PAGE_SHIFT, NULL, + paddr >> VTD_PAGE_SHIFT, + aligned_nrpages(paddr, size), prot); +} + +static struct page * +second_lvl_domain_unmap_range(struct dmar_domain *domain, + unsigned long iova, size_t size) +{ + unsigned long start_pfn, end_pfn, nrpages; + + start_pfn = mm_to_dma_pfn(IOVA_PFN(iova)); + nrpages = aligned_nrpages(iova, size); + end_pfn = start_pfn + nrpages - 1; + + return dma_pte_clear_level(domain, agaw_to_level(domain->agaw), + domain->pgd, 0, start_pfn, end_pfn, NULL); +} + +static phys_addr_t +second_lvl_domain_iova_to_phys(struct dmar_domain *domain, + unsigned long iova) +{ + struct dma_pte *pte; + int level = 0; + u64 phys = 0; + + pte = pfn_to_dma_pte(domain, iova >> VTD_PAGE_SHIFT, &level); + if (pte) + phys = dma_pte_addr(pte); + + return phys; +} + +static void +second_lvl_domain_flush_tlb_range(struct dmar_domain *domain, + struct intel_iommu *iommu, + unsigned long addr, size_t size, + bool ih) +{ + unsigned long pages = aligned_nrpages(addr, size); + u16 did = domain->iommu_did[iommu->seq_id]; + unsigned int mask; + + if (pages) { + mask = ilog2(__roundup_pow_of_two(pages)); + addr &= (u64)-1 << (VTD_PAGE_SHIFT + mask); + } else { + mask = MAX_AGAW_PFN_WIDTH; + addr = 0; + } + + /* + * Fallback to domain selective flush if no PSI support or the size is + * too big. + * PSI requires page size to be 2 ^ x, and the base address is naturally + * aligned to the size + */ + if (!pages || !cap_pgsel_inv(iommu->cap) || + mask > cap_max_amask_val(iommu->cap)) + iommu->flush.iotlb_inv(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); + else + iommu->flush.iotlb_inv(iommu, did, addr | ((int)ih << 6), + mask, DMA_TLB_PSI_FLUSH); + + iommu_flush_dev_iotlb(domain, addr, mask); +} + +static const struct pgtable_ops second_lvl_pgtable_ops = { + .map_range = second_lvl_domain_map_range, + .unmap_range = second_lvl_domain_unmap_range, + .iova_to_phys = second_lvl_domain_iova_to_phys, + .flush_tlb_range = second_lvl_domain_flush_tlb_range, +}; + static int domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, struct scatterlist *sg, unsigned long phys_pfn, unsigned long nr_pages, int prot) -- 2.17.1