From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89DC1C2D0B1 for ; Wed, 4 Dec 2019 20:44:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5B1C62077B for ; Wed, 4 Dec 2019 20:44:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="N6eJkaoo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728306AbfLDUor (ORCPT ); Wed, 4 Dec 2019 15:44:47 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:27724 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727911AbfLDUoq (ORCPT ); Wed, 4 Dec 2019 15:44:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575492285; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RGE10wGHc6+tr5Ix4BO0rOLBP53uaq48GvFVLpjd93I=; b=N6eJkaoo1nxX1uSFB4zMdFIa1u2BlrhZbZ9RU1vxFNd9ykFsJRq67D56o8tWE2EWUtAa6K WF0V4wNSYdSgONz6j15NpUl8HXug/RxNlksQjFMFqyCXDdsweQBaG4caRbwPyHEVEHYHPp vki7Au4dAxDxbiwjQ//Do6gZa21aIfA= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-174-QMcuP3u4OTKTK7Ben7WwpA-1; Wed, 04 Dec 2019 15:44:44 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id CD151107ACC4; Wed, 4 Dec 2019 20:44:42 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 12E5B691A3; Wed, 4 Dec 2019 20:44:39 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, linux-kernel@vger.kernel.org, kvmarm@lists.cs.columbia.edu Cc: james.morse@arm.com, andrew.murray@arm.com, suzuki.poulose@arm.com, drjones@redhat.com Subject: [RFC 1/3] KVM: arm64: pmu: Don't increment SW_INCR if PMCR.E is unset Date: Wed, 4 Dec 2019 21:44:24 +0100 Message-Id: <20191204204426.9628-2-eric.auger@redhat.com> In-Reply-To: <20191204204426.9628-1-eric.auger@redhat.com> References: <20191204204426.9628-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-MC-Unique: QMcuP3u4OTKTK7Ben7WwpA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The specification says PMSWINC increments PMEVCNTR_EL1 by 1 if PMEVCNTR_EL0 is enabled and configured to count SW_INCR. For PMEVCNTR_EL0 to be enabled, we need both PMCNTENSET to be set for the corresponding event counter but we also need the PMCR.E bit to be set. Fixes: 7a0adc7064b8 ("arm64: KVM: Add access handler for PMSWINC register") Signed-off-by: Eric Auger --- virt/kvm/arm/pmu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index 8731dfeced8b..c3f8b059881e 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -486,6 +486,9 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, = u64 val) =09if (val =3D=3D 0) =09=09return; =20 +=09if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E)) +=09=09return; + =09enable =3D __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); =09for (i =3D 0; i < ARMV8_PMU_CYCLE_IDX; i++) { =09=09if (!(val & BIT(i))) --=20 2.20.1