Re: [PATCH v5 13/14] dt-bindings: phy: Document WIZ (SERDES wrapper) bindings

Kishon Vijay Abraham I
2020-01-14T08:04:32Z

Hi Rob,

On 13/01/20 11:29 PM, Rob Herring wrote:
> On Thu, Jan 2, 2020 at 3:54 AM Kishon Vijay Abraham I <kishon@ti.com> wrote:
>>
>> Add DT binding documentation for WIZ (SERDES wrapper). WIZ is *NOT* a
>> PHY but a wrapper used to configure some of the input signals to the
>> SERDES. It is used with both Sierra(16G) and Torrent(10G) serdes.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> [jsarha@ti.com: Add separate compatible for Sierra(16G) and Torrent(10G)
>> SERDES]
>> Signed-off-by: Jyri Sarha <jsarha@ti.com>
>> ---
>> Changes from v4:
>> *) Fixed the indentation as suggested by Rob v4
>>
>> .../bindings/phy/ti,phy-j721e-wiz.yaml | 204 ++++++++++++++++++
>> 1 file changed, 204 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
>> new file mode 100644
>> index 000000000000..e010ea46b88d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
>> @@ -0,0 +1,204 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: TI J721E WIZ (SERDES Wrapper)
>> +
>> +maintainers:
>> + - Kishon Vijay Abraham I <kishon@ti.com>
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - ti,j721e-wiz-16g
>> + - ti,j721e-wiz-10g
>> +
>> + power-domains:
>> + maxItems: 1
>> +
>> + clocks:
>> + maxItems: 3
>> + description: clock-specifier to represent input to the WIZ
>> +
>> + clock-names:
>> + items:
>> + - const: fck
>> + - const: core_ref_clk
>> + - const: ext_ref_clk
>> +
>> + num-lanes:
>> + minimum: 1
>> + maximum: 4
>> +
>> + "#address-cells":
>> + const: 1
>> +
>> + "#size-cells":
>> + const: 1
>> +
>> + "#reset-cells":
>> + const: 1
>> +
>> + ranges: true
>> +
>> + assigned-clocks:
>> + maxItems: 2
>> +
>> + assigned-clock-parents:
>> + maxItems: 2
>> +
>> +patternProperties:
>> + "^pll[0|1]-refclk$":
>> + type: object
>> + description: |
>> + WIZ node should have subnodes for each of the PLLs present in
>> + the SERDES.
>> + properties:
>> + clocks:
>> + maxItems: 2
>> + description: Phandle to clock nodes representing the two inputs to PLL.
>> +
>> + "#clock-cells":
>> + const: 0
>> +
>> + assigned-clocks:
>> + maxItems: 1
>> +
>> + assigned-clock-parents:
>> + maxItems: 1
>> +
>> + required:
>> + - clocks
>> + - "#clock-cells"
>> + - assigned-clocks
>> + - assigned-clock-parents
>> +
>> + "^cmn-refclk1?-dig-div$":
>> + type: object
>> + description:
>> + WIZ node should have subnodes for each of the PMA common refclock
>> + provided by the SERDES.
>> + properties:
>> + clocks:
>> + maxItems: 1
>> + description: Phandle to the clock node representing the input to the
>> + divider clock.
>> +
>> + "#clock-cells":
>> + const: 0
>> +
>> + required:
>> + - clocks
>> + - "#clock-cells"
>> +
>> + "^refclk-dig$":
>> + type: object
>> + description: |
>> + WIZ node should have subnode for refclk_dig to select the reference
>> + clock source for the reference clock used in the PHY and PMA digital
>> + logic.
>> + properties:
>> + clocks:
>> + maxItems: 4
>> + description: Phandle to four clock nodes representing the inputs to
>> + refclk_dig
>> +
>> + "#clock-cells":
>> + const: 0
>> +
>> + assigned-clocks:
>> + maxItems: 1
>> +
>> + assigned-clock-parents:
>> + maxItems: 1
>> +
>> + required:
>> + - clocks
>> + - "#clock-cells"
>> + - assigned-clocks
>> + - assigned-clock-parents
>> +
>> + "^serdes@[0-9a-f]+$":
>> + type: object
>> + description: |
>> + WIZ node should have '1' subnode for the SERDES. It could be either
>> + Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
>> + bindings specified in
>> + Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
>> + Torrent SERDES should follow the bindings specified in
>> + Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
>> +
>> +required:
>> + - compatible
>> + - power-domains
>> + - clocks
>> + - clock-names
>> + - num-lanes
>> + - "#address-cells"
>> + - "#size-cells"
>> + - "#reset-cells"
>> + - ranges
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/soc/ti,sci_pm_domain.h>
>> +
>> + wiz@5000000 {
>> + compatible = "ti,j721e-wiz-16g";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
>> + clock-names = "fck", "core_ref_clk", "ext_ref_clk";
>> + assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
>> + assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
>> + num-lanes = <2>;
>> + #reset-cells = <1>;
>> + ranges = <0x5000000 0x0 0x5000000 0x10000>;
>
> This fails in linux-next:
>
> Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.example.dts:30.16-59:
> Warning (ranges_format): /example-0/wiz@50
> 00000:ranges: "ranges" property has invalid length (16 bytes) (parent
> #address-cells == 1, child #address-cells == 1, #
> size-cells == 1)
>
> Please fix.

Fixed and pushed.

Thanks
Kishon
>
> Rob
>