Re: [PATCH] firmware: qcom: scm: add 32 bit iommu page table support

Rob Clark
2020-01-01T20:14:33Z

On Wed, Jan 1, 2020 at 3:16 AM Stephan Gerhold <stephan@gerhold.net> wrote:
>
> On Tue, Dec 31, 2019 at 10:37:04PM -0500, Brian Masney wrote:
> > Add 32 bit implmentations of the functions
> > __qcom_scm_iommu_secure_ptbl_size() and
> > __qcom_scm_iommu_secure_ptbl_init() that are required by the qcom_iommu
> > driver.
> >
> > Signed-off-by: Brian Masney <masneyb@onstation.org>
> > ---
> > drivers/firmware/qcom_scm-32.c | 32 ++++++++++++++++++++++++++++++--
> > 1 file changed, 30 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c
> > index 48e2ef794ea3..f149a85d36b0 100644
> > --- a/drivers/firmware/qcom_scm-32.c
> > +++ b/drivers/firmware/qcom_scm-32.c
> > @@ -638,13 +638,41 @@ int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
> > int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
> > size_t *size)
> > {
> > - return -ENODEV;
> > + int psize[2] = { 0, 0 };
>
> I would use an explicit size (i.e. __le32) here.
>
> > + int ret;
> > +
> > + ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP,
> > + QCOM_SCM_IOMMU_SECURE_PTBL_SIZE,
> > + &spare, sizeof(spare), &psize, sizeof(psize));
> > + if (ret || psize[1])
> > + return ret ? ret : -EINVAL;
> > +
> > + *size = psize[0];
> > +
> > + return 0;
> > }
> >
> > int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
> > u32 spare)
> > {
> > - return -ENODEV;
> > + struct msm_scm_ptbl_init {
> > + __le32 paddr;
> > + __le32 size;
> > + __le32 spare;
> > + } req;
> > + int ret, scm_ret = 0;
> > +
> > + req.paddr = addr;
> > + req.size = size;
> > + req.spare = spare;
>
> I'm not sure if there is actually anyone using qcom in BE mode (does
> that even work?), but all the other methods in this file explicitly
> convert using cpu_to_le32(), so this method should do the same :)

sboyd used to occasionally fix things related to qcom in BE back in
the day.. not sure if modern snapdragons still support BE.

(I'm willing to just pretend that they don't.. that lessens the chance
that someday someone gets far enough to try the GPU in BE mode, and
realizes they've wasted their time getting that far ;-))

BR,
-R

> > +
> > + ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP,
> > + QCOM_SCM_IOMMU_SECURE_PTBL_INIT,
> > + &req, sizeof(req), &scm_ret, sizeof(scm_ret));
> > + if (ret || scm_ret)
> > + return ret ? ret : -EINVAL;
> > +
> > + return 0;
> > }
> >
> > int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
> > --
> > 2.21.0
> >