Re: [PATCH V3 0/2] PCI: Add MCFG quirks for Tegra194 host controllers

Vidya Sagar
2020-01-16T17:19:28Z

Hi Bjorn,
Could you please review this series?

Thanks in advance,
Vidya Sagar

On 1/11/20 12:44 AM, Vidya Sagar wrote:
> The PCIe controller in Tegra194 SoC is not completely ECAM-compliant.
> With the current hardware design limitations in place, ECAM can be enabled
> only for one controller (C5 controller to be precise) with bus numbers
> starting from 160 instead of 0. A different approach is taken to avoid this
> abnormal way of enabling ECAM for just one controller but to enable
> configuration space access for all the other controllers. In this approach,
> ops are added through MCFG quirk mechanism which access the configuration
> spaces by dynamically programming iATU (internal AddressTranslation Unit)
> to generate respective configuration accesses just like the way it is
> done in DesignWare core sub-system.
> To increase the size of ECAM, a device-tree change is pushed in this series
> to move the IO window from 32-bit PCIe aperture to 64-bit PCIe aperture leaving
> the entire 32MB of 32-bit aperture for configuration space access.
>
> V3:
> * Pushed a device-tree change in the series to enable more space for ECAM
>
> Vidya Sagar (2):
> arm64: tegra: Re-order PCIe aperture mappings to support ACPI boot
> PCI: Add MCFG quirks for Tegra194 host controllers
>
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 36 ++++----
> drivers/acpi/pci_mcfg.c | 7 ++
> drivers/pci/controller/dwc/Kconfig | 3 +-
> drivers/pci/controller/dwc/Makefile | 2 +-
> drivers/pci/controller/dwc/pcie-tegra194.c | 102 +++++++++++++++++++++
> include/linux/pci-ecam.h | 1 +
> 6 files changed, 131 insertions(+), 20 deletions(-)
>