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[79.183.34.164]) by smtp.gmail.com with ESMTPSA id o55sm3628837qtf.46.2020.01.09.08.47.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jan 2020 08:47:31 -0800 (PST) Date: Thu, 9 Jan 2020 11:47:25 -0500 From: "Michael S. Tsirkin" To: "Liu, Jiang" Cc: Jason Wang , Zha Bin , linux-kernel@vger.kernel.org, slp@redhat.com, virtio-dev@lists.oasis-open.org, jing2.liu@intel.com, chao.p.peng@intel.com Subject: Re: [PATCH v1 2/2] virtio-mmio: add features for virtio-mmio specification version 3 Message-ID: <20200109114209-mutt-send-email-mst@kernel.org> References: <229e689d-10f1-2bfb-c393-14dfa9c78971@redhat.com> <0460F92A-3DF6-4F7A-903B-6434555577CC@linux.alibaba.com> <56703BDA-B7AE-4656-8061-85FD1A130597@linux.alibaba.com> <20200105054142-mutt-send-email-mst@kernel.org> <02D38CC0-8DD5-44E1-92B2-0F9E97A112CE@linux.alibaba.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <02D38CC0-8DD5-44E1-92B2-0F9E97A112CE@linux.alibaba.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jan 10, 2020 at 12:06:06AM +0800, Liu, Jiang wrote: > On Jan 5, 2020, at 6:42 PM, Michael S. Tsirkin wrote: > > > > On Thu, Dec 26, 2019 at 09:16:19PM +0800, Liu, Jiang wrote: > >>> 2) The mask and unmask control is missed > >>> > >>> > >>>> but the extension doesn’t support 3) because > >>>> we noticed that the Linux virtio subsystem doesn’t really make use of interrupt masking/unmasking. > > > > Linux uses masking/unmasking in order to migrate interrupts between > > CPUs. > This is a limitation of the PCI MSI/MSIx spec. > To update the MSI/MSIx vector configuration, we need to write to msg_high/msg_low/msg_data registers. > Because write to three 32-bit registers is not an atomic operation on PCI bus, so it may cause incorrect interrupt delivery if interrupt happens after writing 1 or 2 registers. > When Intel remapping is enabled on x86 platforms, we don’t need to mask/unmask PCI MSI/MSIx interrupts when setting affinity. > For MMIO MSI extension, we have special design to solve this race window. The flow to update MMIO MSI vector configuration is: > 1) write msg_high > 2) write msg_low > 3) write msg_data > 4) write the command register to update the vector configuration. > During step 1-3, the hardware/device backend driver only caches the value written. And update the vector configuration in step 4, so it’s an atomic operation now. > So mask/unmask becomes optional for MMIO MSI interrupts. Oh I see. That needs some documentation I guess. One question though: how do you block VQ from generating interrupts? There's value in doing that for performance since then device can avoid re-checking interrupt enable/event idx values in memory. > > > > -- > > MST