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[157.230.128.187]) by smtp.gmail.com with ESMTPSA id v9sm504680pja.26.2020.01.15.10.58.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 10:58:14 -0800 (PST) Received: by 42.do-not-panic.com (Postfix, from userid 1000) id 7338E40244; Wed, 15 Jan 2020 18:58:12 +0000 (UTC) Date: Wed, 15 Jan 2020 18:58:12 +0000 From: Luis Chamberlain To: Jari Ruusu Cc: Borislav Petkov , Fenghua Yu , Linus Torvalds , johannes.berg@intel.com, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Hans de Goede , Andy Lutomirski Subject: Re: Fix built-in early-load Intel microcode alignment Message-ID: <20200115185812.GH11244@42.do-not-panic.com> References: <20200113154739.GB11244@42.do-not-panic.com> <20200115021545.GD11244@42.do-not-panic.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jan 15, 2020 at 08:46:04PM +0200, Jari Ruusu wrote: > On 1/15/20, Luis Chamberlain wrote: > > On Mon, Jan 13, 2020 at 09:58:25PM +0200, Jari Ruusu wrote: > >> Before that 16-byte alignment patch was applied, my only one > >> microcode built-in BLOB was "accidentally" 16-byte aligned. > > > > How did it accidentially get 16-byte aligned? > > Old code aligned it to 8-bytes. > There is 50/50-chance of it also being 16-byte aligned. But *how? Why is there a 50/50 chance of it being aligned to 16 bytes if 8 bytes are currently specified? > So it ended up being both 8-byte and 16-byte aligned. What do you mean both? How can it be aligned to both? > > Also, how do you *know* something is broken right now? > > I haven't spotted brokenness in Linux microcode loader other > than that small alignment issue. > > However, I can confirm that there are 2 microcode updates newer > than what my laptop computer's latest BIOS includes. Both newer > ones (20191115 and 20191112) are unstable on my laptop computer > i5-7200U (fam 6 model 142 step 9 pf 0x80). Hard lockups with both > of them. Back to BIOS microcode for now. I was more interested in how you are *certain*, other than manualcode inspection, and that a spec indicates we should use 16 bytes for Intel microcode -- that the 8 byte alignment *does* not allow users to currently update their Intel CPU microcode for built-in firmware. >From what I gather so far we have no case yet reported where we know for sure it fails right now with the 8 byte alignment on 64-bit. This information would just be useful for the commit log. Luis