From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67388C33CB6 for ; Thu, 16 Jan 2020 18:56:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 43BF52053B for ; Thu, 16 Jan 2020 18:56:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1579200973; bh=bNiy90xVJRfMzT44s3VPJaM+fSR6I0X0QorvYOHR/GQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=AZehOXpGLZRoguDindVZ8EgEwEnAMTfCzpPHnttgqvp7dvIQNur//VJfDnc8Hf5C0 npwCzeIXBMGbZi1LkByRK13+yjHDWfKNf4epIVx0ZvT042WMhybQXrJn0MwoIhc7TE TLERFJEjFrcNVmgMNTCakJii+sTi/bUyRsA8FJUE= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388419AbgAPRH1 (ORCPT ); Thu, 16 Jan 2020 12:07:27 -0500 Received: from mail.kernel.org ([198.145.29.99]:38872 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388187AbgAPRHR (ORCPT ); Thu, 16 Jan 2020 12:07:17 -0500 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 01D352081E; Thu, 16 Jan 2020 17:07:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1579194436; bh=bNiy90xVJRfMzT44s3VPJaM+fSR6I0X0QorvYOHR/GQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SI5UCTYXWNVVGVjOu8e0oQA/35bfgXOU0JBznucK7poyUPKuuK4X1d7QsHCNamHfY jv6/pu9R+xVHCdQLZwggB6YWQ6hV8lf/mZtmQ+f1knxu41XpIkA5meY1n+HRABB/dy vxnVS1Yug8yYw8fXVWNdItQCPEdXeMnvNrqYMNLE= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Martin Blumenstingl , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Neil Armstrong , Thierry Reding , Sasha Levin , linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org Subject: [PATCH AUTOSEL 4.19 350/671] pwm: meson: Consider 128 a valid pre-divider Date: Thu, 16 Jan 2020 11:59:48 -0500 Message-Id: <20200116170509.12787-87-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200116170509.12787-1-sashal@kernel.org> References: <20200116170509.12787-1-sashal@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Martin Blumenstingl [ Upstream commit 51496e4446875726d50a5617a6e0e0dabbc2e6da ] The pre-divider allows configuring longer PWM periods compared to using the input clock directly. The pre-divider is 7 bit wide, meaning it's maximum value is 128 (the register value is off-by-one: 0x7f or 127). Change the loop to also allow for the maximum possible value to be considered valid. Fixes: 211ed630753d2f ("pwm: Add support for Meson PWM Controller") Signed-off-by: Martin Blumenstingl Acked-by: Uwe Kleine-König Reviewed-by: Neil Armstrong Signed-off-by: Thierry Reding Signed-off-by: Sasha Levin --- drivers/pwm/pwm-meson.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index f6e738ad7bd9..4b708c1fcb1d 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -188,7 +188,7 @@ static int meson_pwm_calc(struct meson_pwm *meson, do_div(fin_ps, fin_freq); /* Calc pre_div with the period */ - for (pre_div = 0; pre_div < MISC_CLK_DIV_MASK; pre_div++) { + for (pre_div = 0; pre_div <= MISC_CLK_DIV_MASK; pre_div++) { cnt = DIV_ROUND_CLOSEST_ULL((u64)period * 1000, fin_ps * (pre_div + 1)); dev_dbg(meson->chip.dev, "fin_ps=%llu pre_div=%u cnt=%u\n", @@ -197,7 +197,7 @@ static int meson_pwm_calc(struct meson_pwm *meson, break; } - if (pre_div == MISC_CLK_DIV_MASK) { + if (pre_div > MISC_CLK_DIV_MASK) { dev_err(meson->chip.dev, "unable to get period pre_div\n"); return -EINVAL; } -- 2.20.1