Re: [RESEND PATCH] perf/x86/intel: Fix inaccurate period in context switch for auto-reload

Liang, Kan
2020-01-17T15:13:46Z

On 1/17/2020 3:58 AM, Peter Zijlstra wrote:
> On Thu, Jan 16, 2020 at 10:31:54AM -0800, kan.liang@linux.intel.com wrote:
>> From: Kan Liang <kan.liang@linux.intel.com>
>>
>> Perf doesn't take the left period into account when auto-reload is
>> enabled with fixed period sampling mode in context switch.
>> Here is the ftrace when recording PEBS event with fixed period.
>>
>> #perf record -e cycles:p -c 2000000 -- ./triad_loop
>>
>> //Task is scheduled out
>> triad_loop-17222 [000] d... 861765.878032: write_msr:
>> MSR_CORE_PERF_GLOBAL_CTRL(38f), value 0 //Disable global counter
>> triad_loop-17222 [000] d... 861765.878033: write_msr:
>> MSR_IA32_PEBS_ENABLE(3f1), value 0 //Disable PEBS
>> triad_loop-17222 [000] d... 861765.878033: write_msr:
>> MSR_P6_EVNTSEL0(186), value 40003003c //Disable the counter
>> triad_loop-17222 [000] d... 861765.878033: rdpmc: 0, value
>> fffffff82840 //Read value of the counter
>> triad_loop-17222 [000] d... 861765.878034: write_msr:
>> MSR_CORE_PERF_GLOBAL_CTRL(38f), value 1000f000000ff //Re-enable global
>> counter
>
> This is unreadable garbage, please don't wrap trace output.
>

Sorry for that.
I will make the log clear in V2.

Thanks,
Kan