From: Peter Zijlstra <peterz@infradead.org>
To: kan.liang@linux.intel.com
Cc: acme@redhat.com, mingo@kernel.org, linux-kernel@vger.kernel.org,
ak@linux.intel.com, eranian@google.com
Subject: Re: [RESEND PATCH V2] perf/x86/intel: Avoid unnecessary PEBS_ENABLE MSR access in PMI
Date: Fri, 17 Jan 2020 09:54:12 +0100 [thread overview]
Message-ID: <20200117085412.GU2827@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20200116182112.20782-1-kan.liang@linux.intel.com>
On Thu, Jan 16, 2020 at 10:21:12AM -0800, kan.liang@linux.intel.com wrote:
> A PMI may land after cpuc->enabled=0 in x86_pmu_disable() and
> PMI throttle may be triggered for the PMI. For this rare case,
> intel_pmu_pebs_disable() will not touch PEBS_ENABLE MSR. The patch
> explicitly disable the PEBS for this case.
intel_pmu_handle_irq()
pmu_enabled = cpuc->enabled;
cpuc->enabled = 0;
__intel_pmu_disable_all();
...
x86_pmu_stop()
intel_pmu_disable_event()
intel_pmu_pebs_disable()
if (cpuc->enabled) // FALSE!!!
cpuc->enabled = pmu_enabled;
if (pmu_enabled)
__intel_pmu_enable_all();
> @@ -2620,6 +2627,15 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status)
> handled++;
> x86_pmu.drain_pebs(regs);
> status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
> +
> + /*
> + * PMI may land after cpuc->enabled=0 in x86_pmu_disable() and
> + * PMI throttle may be triggered for the PMI.
> + * For this rare case, intel_pmu_pebs_disable() will not touch
> + * MSR_IA32_PEBS_ENABLE. Explicitly disable the PEBS here.
> + */
> + if (unlikely(!cpuc->enabled && !cpuc->pebs_enabled))
> + wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
> }
How does that make sense? AFAICT this is all still completely broken.
Please be more careful.
next prev parent reply other threads:[~2020-01-17 8:54 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-16 18:21 [RESEND PATCH V2] perf/x86/intel: Avoid unnecessary PEBS_ENABLE MSR access in PMI kan.liang
2020-01-17 8:54 ` Peter Zijlstra [this message]
2020-01-17 15:10 ` Liang, Kan
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