From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.7 required=3.0 tests=DATE_IN_PAST_03_06, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECB0BC2D0DB for ; Wed, 22 Jan 2020 13:27:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B58B324688 for ; Wed, 22 Jan 2020 13:27:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1579699635; bh=bVmEqRxthyQil9CBv5ZYY8CyvuaiSbMYuOTK0Pqlna8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=O9JBPHp0+se5bMw3CuNQo2cvv8hMMAeoIOsAW9f7ebXbsggi4Sh/x+DZgb/eBWeHc n4WCo5Eo2Tk8nO7Rm7Utite4VwIhcEndYme7j51pJRWDJZ00+cz61giW7UMg7BsLMr EuQ5oUM+leMq0luBLyc114fCEharXMXvuzMEbcXE= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730357AbgAVN1O (ORCPT ); Wed, 22 Jan 2020 08:27:14 -0500 Received: from mail.kernel.org ([198.145.29.99]:48326 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729332AbgAVN1H (ORCPT ); Wed, 22 Jan 2020 08:27:07 -0500 Received: from localhost (unknown [84.241.205.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8D24624685; Wed, 22 Jan 2020 13:27:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1579699627; bh=bVmEqRxthyQil9CBv5ZYY8CyvuaiSbMYuOTK0Pqlna8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uTd54wRXV6BsZrBhfS+h798QhvtQE2JK7yTBQiGw/iwdv733NEAIceuClo9TPjFbM 3DXGLRJB1DstvtkuAR156FEMw2i2sZkNVWBVAPXotYa8W18rhftN69hGMJnLw3LLZH uwByTeKqEp79ul0HGLUM6iCr3mVm1s5T2SenLx6E= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Xiang Chen , John Garry , "Martin K. Petersen" Subject: [PATCH 5.4 201/222] scsi: hisi_sas: Set the BIST init value before enabling BIST Date: Wed, 22 Jan 2020 10:29:47 +0100 Message-Id: <20200122092848.097671225@linuxfoundation.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200122092833.339495161@linuxfoundation.org> References: <20200122092833.339495161@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen commit 65a3b8bd56942dc988b8c05615bd3f510a10012b upstream. If set the BIST init value after enabling BIST, there may be still some few error bits. According to the process, need to set the BIST init value before enabling BIST. Fixes: 97b151e75861 ("scsi: hisi_sas: Add BIST support for phy loopback") Link: https://lore.kernel.org/r/1571926105-74636-3-git-send-email-john.garry@huawei.com Signed-off-by: Xiang Chen Signed-off-by: John Garry Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -3022,11 +3022,6 @@ static int debugfs_set_bist_v3_hw(struct hisi_sas_phy_write32(hisi_hba, phy_id, SAS_PHY_BIST_CTRL, reg_val); - mdelay(100); - reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK); - hisi_sas_phy_write32(hisi_hba, phy_id, - SAS_PHY_BIST_CTRL, reg_val); - /* set the bist init value */ hisi_sas_phy_write32(hisi_hba, phy_id, SAS_PHY_BIST_CODE, @@ -3035,6 +3030,11 @@ static int debugfs_set_bist_v3_hw(struct SAS_PHY_BIST_CODE1, SAS_PHY_BIST_CODE1_INIT); + mdelay(100); + reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK); + hisi_sas_phy_write32(hisi_hba, phy_id, + SAS_PHY_BIST_CTRL, reg_val); + /* clear error bit */ mdelay(100); hisi_sas_phy_read32(hisi_hba, phy_id, SAS_BIST_ERR_CNT);