Re: [PATCH v2] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines

Florian Fainelli
2020-02-07T22:35:55Z

On 2/7/20 2:33 PM, Kamal Dasu wrote:
> Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache
> line can contain two instruction cache lines (64B), or four data cache
> lines (32B). Hardware prefetch Cache detects stream access, and prefetches
> ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr
> secondary cache module (ZSCM) on DMA from device so that data returned is
> coherent during DMA read operations.
>
> Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>

Thanks Kamal!
--
Florian