RE: [PATCH RFC 0/7] perf pmu-events: Support event aliasing for system PMUs

Joakim Zhang
2020-02-19T12:40:27Z

> -----Original Message-----
> From: John Garry <john.garry@huawei.com>
> Sent: 2020年2月19日 16:44
> To: Joakim Zhang <qiangqing.zhang@nxp.com>; Mark Rutland
> <mark.rutland@arm.com>
> Cc: ak@linux.intel.com; suzuki.poulose@arm.com; peterz@infradead.org; Will
> Deacon <will@kernel.org>; Linuxarm <linuxarm@huawei.com>;
> acme@kernel.org; linux-kernel@vger.kernel.org; Zhangshaokun
> <zhangshaokun@hisilicon.com>; alexander.shishkin@linux.intel.com;
> mingo@redhat.com; james.clark@arm.com; namhyung@kernel.org;
> jolsa@redhat.com; linux-arm-kernel@lists.infradead.org;
> robin.murphy@arm.com; Sudeep Holla <sudeep.holla@arm.com>
> Subject: Re: [PATCH RFC 0/7] perf pmu-events: Support event aliasing for
> system PMUs
>
> On 19/02/2020 01:55, Joakim Zhang wrote:
> >
> >> -----Original Message-----
> >> From: Mark Rutland <mark.rutland@arm.com>
> >> Sent: 2020年2月19日 2:14
> >> To: John Garry <john.garry@huawei.com>
> >> Cc: ak@linux.intel.com; Joakim Zhang <qiangqing.zhang@nxp.com>;
> >> suzuki.poulose@arm.com; peterz@infradead.org; Will Deacon
> >> <will@kernel.org>; Linuxarm <linuxarm@huawei.com>; acme@kernel.org;
> >> linux-kernel@vger.kernel.org; Zhangshaokun
> >> <zhangshaokun@hisilicon.com>; alexander.shishkin@linux.intel.com;
> >> mingo@redhat.com; james.clark@arm.com; namhyung@kernel.org;
> >> jolsa@redhat.com; linux-arm-kernel@lists.infradead.org;
> >> robin.murphy@arm.com; Sudeep Holla <sudeep.holla@arm.com>
> >> Subject: Re: [PATCH RFC 0/7] perf pmu-events: Support event aliasing
> >> for system PMUs
> >
> > [...]
> >>> And typically most PMU HW would have no ID reg, so where to even get
> >>> this identification info? Joakim Zhang seems to have this problem
> >>> for the imx8 DDRC PMU driver.
> >>
> >> For imx8, the DT compat string or additional properties on the DDRC
> >> node could be used to imply the id.
> >
> > Hi Mark,
> >
> > Yes, actually we can expose something like DDRC_ID to indicate each specific
> DDR controller, to point out the filter feature.
> > But, even the SoCs integrated the same DDRC_ID, just say that they have the
> same DDRC controller.
> >
> > From user space, the usage is different, for example:
> >
> > i.MX8MM and i.MX8MN, they use the same driver(DDRC_ID) and cortex-a53
> integrated.
> >
> > If we want to monitor VPU, their *master id* is different from SoCs.
> > On i.MX8MM, event is imx8_ddr0/axid-read,axi_id=0x08/ On i.MX8MN,
> > event is imx8_ddr0/axid-read,axi_id=0x12/
> >
> > I try to write a JSON file to use these events, for now, I only can
> > locate the file at the directory:
> > tools/perf/pmu-events/arch/arm64/arm/cortex-a53/
> >
> > Perf tool loads all events when CPUID matched, which is now unreasonable,
> we want related events are loaded for specific SoC.
>
> so we could have a folder like .../arch/arm64/nxp/system for these JSONs. The
> perf tool can be updated to handle CPU and system events in separate folders.
>
> >
> > All events will also be loaded if we use DDRC_ID to match in the future, this
> seems to not be a good ideal.
>
> The important part is knowing which events are supported per implementation.
> Is there any method in the driver of knowing the specific implementation, like
> any DT compat string? Least preferred option would be DT machine ID.

I think, NO, master id could be different even they use the same DT compatible string.

Best Regards,
Joakim Zhang
> >
>
> John