[PATCH 0/7] microblaze: Define SMP safe operations

Michal Simek
2020-02-12T15:42:34Z

Hi,

This is follow up series on the top of cleanup series available here.
https://lkml.org/lkml/2020/2/12/215
There are two things together.
1. Changes in cpuinfo structure in patches 1 and 2
2. Defining SMP safe operations instead of IRQ disabling

Microblaze has 32bit exclusive load/store instructions which should be used
instead of irq enable/disable. For more information take a look at
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug984-vivado-microblaze-ref.pdf
starting from page 25.

Thanks,
Michal

Michal Simek (1):
microblaze: timer: Don't use cpu timer setting

Stefan Asserhall (5):
microblaze: Make cpuinfo structure SMP aware
microblaze: Define SMP safe bit operations
microblaze: Add SMP implementation of xchg and cmpxchg
microblaze: Remove disabling IRQ while pte_update() run
microblaze: Implement architecture spinlock

Stefan Asserhall load and store (1):
microblaze: Do atomic operations by using exclusive ops

arch/microblaze/include/asm/Kbuild | 1 -
arch/microblaze/include/asm/atomic.h | 265 ++++++++++++++++++-
arch/microblaze/include/asm/bitops.h | 189 +++++++++++++
arch/microblaze/include/asm/cmpxchg.h | 87 ++++++
arch/microblaze/include/asm/cpuinfo.h | 2 +-
arch/microblaze/include/asm/pgtable.h | 19 +-
arch/microblaze/include/asm/spinlock.h | 240 +++++++++++++++++
arch/microblaze/include/asm/spinlock_types.h | 25 ++
arch/microblaze/kernel/cpu/cache.c | 154 ++++++-----
arch/microblaze/kernel/cpu/cpuinfo.c | 38 ++-
arch/microblaze/kernel/cpu/mb.c | 207 ++++++++-------
arch/microblaze/kernel/timer.c | 2 +-
arch/microblaze/mm/consistent.c | 8 +-
13 files changed, 1040 insertions(+), 197 deletions(-)
create mode 100644 arch/microblaze/include/asm/bitops.h
create mode 100644 arch/microblaze/include/asm/spinlock.h
create mode 100644 arch/microblaze/include/asm/spinlock_types.h

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2.25.0