From: Peter Zijlstra <peterz@infradead.org>
To: Will Deacon <will@kernel.org>
Cc: Michal Simek <michal.simek@xilinx.com>,
linux-kernel@vger.kernel.org, monstr@monstr.eu, git@xilinx.com,
arnd@arndb.de,
Stefan Asserhall load and store <stefan.asserhall@xilinx.com>,
Boqun Feng <boqun.feng@gmail.com>,
paulmck@kernel.org
Subject: Re: [PATCH 7/7] microblaze: Do atomic operations by using exclusive ops
Date: Thu, 13 Feb 2020 11:15:38 +0100 [thread overview]
Message-ID: <20200213101538.GN14897@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20200213100403.GA1405@willie-the-truck>
On Thu, Feb 13, 2020 at 10:04:03AM +0000, Will Deacon wrote:
> On Thu, Feb 13, 2020 at 10:16:51AM +0100, Peter Zijlstra wrote:
> > On Thu, Feb 13, 2020 at 09:58:49AM +0100, Peter Zijlstra wrote:
> >
> > > The thing is, your bog standard LL/SC _SHOULD_ fail the SC if someone
> > > else does a regular store to the same variable. See the example in
> > > Documentation/atomic_t.txt.
> > >
> > > That is, a competing SW/SWI should result in the interconnect responding
> > > with something other than EXOKAY, the SWX should fail and MSR[C] <- 1.
> >
> > The thing is; we have code that relies on this behaviour. There are a
> > few crusty SMP archs that sorta-kinda limp along (mostly by disabling
> > some of the code and praying the rest doesn't trigger too often), but we
> > really should not allow more broken SMP archs.
>
> I did find this in the linked pdf:
>
> | If the store [swx] is successful, the sequence of instructions from
> | the semaphore load to the semaphore store appear to be executed
> | atomically - no other device modified the semaphore location between
> | the read and the update.
>
> which sounds like we're ok, although it could be better worded.
>
> One part I haven't figured out is what happens if you take an interrupt
> between the lwx and the swx and whether you can end up succeeding thanks
> to somebody else's reservation. Also, the manual is silent about the
> interaction with TLB invalidation and just refers to "address" when
> talking about the reservation. What happens if a user thread triggers
> CoW while another is in the middle of a lwx/swx?
Page 79, Table 2-40 has the note:
"All of these events will clear the reservation bit, used together with
the LWX and SWX instructions to implement mutual exclusion,..."
next prev parent reply other threads:[~2020-02-13 10:15 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-12 15:42 [PATCH 0/7] microblaze: Define SMP safe operations Michal Simek
2020-02-12 15:42 ` [PATCH 1/7] microblaze: timer: Don't use cpu timer setting Michal Simek
2020-02-12 15:42 ` [PATCH 2/7] microblaze: Make cpuinfo structure SMP aware Michal Simek
2020-02-12 20:42 ` Arnd Bergmann
2020-02-12 15:42 ` [PATCH 3/7] microblaze: Define SMP safe bit operations Michal Simek
2020-02-12 15:53 ` Peter Zijlstra
2020-02-13 8:42 ` Michal Simek
2020-02-13 9:01 ` Stefan Asserhall
2020-02-13 9:11 ` Peter Zijlstra
2020-02-13 9:24 ` Stefan Asserhall
2020-02-12 15:42 ` [PATCH 4/7] microblaze: Add SMP implementation of xchg and cmpxchg Michal Simek
2020-02-12 15:42 ` [PATCH 5/7] microblaze: Remove disabling IRQ while pte_update() run Michal Simek
2020-02-12 15:42 ` [PATCH 6/7] microblaze: Implement architecture spinlock Michal Simek
2020-02-12 15:47 ` Peter Zijlstra
2020-02-13 7:51 ` Michal Simek
2020-02-13 8:00 ` Peter Zijlstra
2020-02-12 15:42 ` [PATCH 7/7] microblaze: Do atomic operations by using exclusive ops Michal Simek
2020-02-12 15:55 ` Peter Zijlstra
2020-02-13 8:06 ` Michal Simek
2020-02-13 8:58 ` Peter Zijlstra
2020-02-13 9:16 ` Peter Zijlstra
2020-02-13 10:04 ` Will Deacon
2020-02-13 10:14 ` Stefan Asserhall
2020-02-13 10:20 ` Will Deacon
2020-02-13 10:15 ` Peter Zijlstra [this message]
2020-02-13 11:34 ` Boqun Feng
2020-02-13 11:38 ` Boqun Feng
2020-02-13 13:51 ` Andrea Parri
2020-02-13 14:01 ` Andrea Parri
2020-02-12 16:08 ` [PATCH 0/7] microblaze: Define SMP safe operations Peter Zijlstra
2020-02-12 16:38 ` Peter Zijlstra
2020-02-13 7:49 ` Michal Simek
2020-02-13 8:11 ` Peter Zijlstra
2020-02-13 8:12 ` Michal Simek
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