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From: Mark Brown <broonie@kernel.org>
To: "Ramuthevar,Vadivel MuruganX" 
	<vadivel.muruganx.ramuthevar@linux.intel.com>
Cc: linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
	vigneshr@ti.com, mark.rutland@arm.com, robh+dt@kernel.org,
	devicetree@vger.kernel.org, dan.carpenter@oracle.com,
	cheol.yong.kim@intel.com, qi-ming.wu@intel.com
Subject: Re: [PATCH v9 2/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller
Date: Fri, 14 Feb 2020 13:09:52 +0000	[thread overview]
Message-ID: <20200214130952.GI4827@sirena.org.uk> (raw)
In-Reply-To: <20200214114618.29704-3-vadivel.muruganx.ramuthevar@linux.intel.com>

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On Fri, Feb 14, 2020 at 07:46:18PM +0800, Ramuthevar,Vadivel MuruganX wrote:

> +static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
> +{
> +	struct cqspi_st *cqspi = dev;
> +	unsigned int irq_status;
> +
> +	/* Read interrupt status */
> +	irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
> +
> +	/* Clear interrupt */
> +	writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
> +
> +	irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
> +
> +	if (irq_status)
> +		complete(&cqspi->transfer_complete);
> +
> +	return IRQ_HANDLED;
> +}

This will unconditionally handle the interrupt regardless of if the
hardware was actually flagging an interrupt which will break shared
interrupts and the fault handling code in genirq.

> +	tmpbufsize = op->addr.nbytes + op->dummy.nbytes;
> +	tmpbuf = kzalloc(tmpbufsize, GFP_KERNEL | GFP_DMA);
> +	if (!tmpbuf)
> +		return -ENOMEM;

I'm not clear where tmpbuf gets freed or passed out of this function?

> +
> +	if (op->addr.nbytes) {
> +		for (i = 0; i < op->addr.nbytes; i++)
> +			tmpbuf[i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
> +
> +		addr_buf = tmpbuf;

We assign tmpbuf to addr_buf here but addr_buf just gets read from so
it's not via that AFAICT.

> +	}
> +	/* Invalid address return zero. */

Missing blank line.

> +static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata)
> +{
> +	struct cqspi_st *cqspi = f_pdata->cqspi;
> +	void __iomem *reg_base = cqspi->iobase;
> +	unsigned int chip_select = f_pdata->cs;
> +	unsigned int reg;
> +
> +	reg = readl(reg_base + CQSPI_REG_CONFIG);
> +	reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
> +
> +	/* Convert CS if without decoder.
> +	 * CS0 to 4b'1110
> +	 * CS1 to 4b'1101
> +	 * CS2 to 4b'1011
> +	 * CS3 to 4b'0111
> +	 */
> +	chip_select = 0xF & ~(1 << chip_select);

This says "if without decoder" but there's no conditionals here, what if
we do have a decoder?

> +	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
> +	ddata  = of_device_get_match_data(dev);
> +	if (ddata) {
> +		if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
> +			cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
> +						cqspi->master_ref_clk_hz);
> +		if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
> +			master->mode_bits |= SPI_RX_OCTAL;
> +		if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE))
> +			cqspi->use_dac_mode = true;
> +		if (ddata->quirks & CQSPI_NEEDS_ADDR_SWAP) {
> +			master->bus_num = 0;
> +			master->num_chipselect = 2;
> +		}
> +	}

Given that the driver appears to unconditionally dereference match data
in other places I'd expect this to return an error if there's none,
otherwise we'll oops in those other code paths later on.

> +	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
> +			       pdev->name, cqspi);
> +	if (ret) {
> +		dev_err(dev, "Cannot request IRQ.\n");
> +		goto probe_reset_failed;
> +	}

Are you sure that it's safe to use devm_request_irq() - what happens if
the interrupt fires in the process of removing the device?

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  reply	other threads:[~2020-02-14 13:09 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-14 11:46 [PATCH v9 0/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller Ramuthevar,Vadivel MuruganX
2020-02-14 11:46 ` [PATCH v9 1/2] dt-bindings: spi: Add schema for Cadence QSPI Controller driver Ramuthevar,Vadivel MuruganX
2020-02-14 14:08   ` Mark Brown
2020-02-14 11:46 ` [PATCH v9 2/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller Ramuthevar,Vadivel MuruganX
2020-02-14 13:09   ` Mark Brown [this message]
2020-02-17  9:18     ` Ramuthevar, Vadivel MuruganX
2020-02-17 17:09       ` Mark Brown
2020-02-18  3:17         ` Ramuthevar, Vadivel MuruganX
2020-02-14 12:02 ` [PATCH v9 0/2] " Simon Goldschmidt
2020-02-14 12:11   ` Mark Brown
2020-02-14 12:50     ` Simon Goldschmidt
2020-02-14 13:15       ` Mark Brown
2020-02-14 13:49         ` Simon Goldschmidt
2020-02-14 14:16           ` Mark Brown
2020-02-17 10:09     ` Ramuthevar, Vadivel MuruganX
     [not found]     ` <4712cdc4-34cd-990b-3d53-3d394ae1250b@linux.intel.com>
2020-02-17 11:52       ` Mark Brown
2020-02-17 12:18         ` Vignesh Raghavendra
2020-02-18  8:56           ` Ramuthevar, Vadivel MuruganX
2020-02-17 10:11   ` Ramuthevar, Vadivel MuruganX

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