From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.4 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BA1CC3F2D1 for ; Mon, 2 Mar 2020 09:54:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 23A1421D56 for ; Mon, 2 Mar 2020 09:54:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="n8wx694Z" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727517AbgCBJyN (ORCPT ); Mon, 2 Mar 2020 04:54:13 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:50012 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727060AbgCBJyM (ORCPT ); Mon, 2 Mar 2020 04:54:12 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0229rlXE038637; Mon, 2 Mar 2020 03:53:47 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1583142827; bh=MaPO+Y+GFt8NojyCTT0VA83fEm+Nn1m3L1ToA+6WYhk=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=n8wx694Zu850t8rho+LltUhbikx5WUkA5L6N7d1S0Uxo+N7tAk8V8nj0E6CsXohLq V0yjLlqMWSuyTlFVIkSZM5CTsb/W7QhWErbHvvYfpoHA9QJCi4pXF5uPoVfTviXUle Sw3XNYzuziw8iYcrh0aXMLK5Yy4mY7Rh06njFALE= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0229rkWa040407 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Mar 2020 03:53:47 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 2 Mar 2020 03:53:46 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 2 Mar 2020 03:53:46 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0229rjSg028864; Mon, 2 Mar 2020 03:53:46 -0600 Date: Mon, 2 Mar 2020 15:23:45 +0530 From: Pratyush Yadav To: Geert Uytterhoeven CC: Mark Brown , Boris Brezillon , Mark Rutland , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Vignesh Raghavendra , Tudor Ambarus , Richard Weinberger , Sekhar Nori , Linux Kernel Mailing List , linux-spi , Rob Herring , MTD Maling List , Miquel Raynal Subject: Re: [PATCH v2 01/11] dt-bindings: spi: allow expressing DTR capability Message-ID: <20200302095343.3yec6inur52vx6bg@ti.com> References: <20200226093703.19765-1-p.yadav@ti.com> <20200226093703.19765-2-p.yadav@ti.com> <20200227171147.32cc6fcf@collabora.com> <20200227162842.GE4062@sirena.org.uk> <20200227164425.GF4062@sirena.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 27/02/20 06:03PM, Geert Uytterhoeven wrote: > Hi Mark, > > On Thu, Feb 27, 2020 at 5:44 PM Mark Brown wrote: > > On Thu, Feb 27, 2020 at 05:40:31PM +0100, Geert Uytterhoeven wrote: > > > On Thu, Feb 27, 2020 at 5:28 PM Mark Brown wrote: > > > > It's what we do for other properties, and if this is anything like the > > > > other things adding extra wiring you can't assume that the ability to > > > > use the feature for TX implies RX. > > > > > Double Transfer Rate uses the same wire. > > > > But is it still on either the TX or RX signals? > > E.g. good old Spansion S25FL512S supports single/dual/quad DDR, but > apparently only for read, not write. > Other FLASHes may support both directions. I guess. The flash datasheet says under section 9.4 (Read Memory Array Commands): Some commands transfer address and data on both the rising edge and falling edge of SCK. These are called Double Data Rate (DDR) commands. Since the address is transferred in DDR mode, both Tx and Rx signals use DDR. So, unless we have a flash that supports a mode like 1S-1S-8D, we don't really need two properties. -- Regards, Pratyush Yadav Texas Instruments India