From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0F5CC10DCE for ; Wed, 18 Mar 2020 17:57:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AEAE820767 for ; Wed, 18 Mar 2020 17:57:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726752AbgCRR5M (ORCPT ); Wed, 18 Mar 2020 13:57:12 -0400 Received: from foss.arm.com ([217.140.110.172]:52872 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726506AbgCRR5M (ORCPT ); Wed, 18 Mar 2020 13:57:12 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D09A01FB; Wed, 18 Mar 2020 10:57:11 -0700 (PDT) Received: from arrakis.emea.arm.com (arrakis.cambridge.arm.com [10.1.196.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 11E303F67D; Wed, 18 Mar 2020 10:57:10 -0700 (PDT) Date: Wed, 18 Mar 2020 17:57:09 +0000 From: Catalin Marinas To: =?iso-8859-1?Q?R=E9mi?= Denis-Courmont Cc: will@kernel.org, linux-arm-kernel@lists.infradead.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/3] arm64: clean up trampoline vector loads Message-ID: <20200318175709.GD94111@arrakis.emea.arm.com> References: <20200316124046.103844-1-remi@remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20200316124046.103844-1-remi@remlab.net> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 16, 2020 at 02:40:44PM +0200, Rémi Denis-Courmont wrote: > From: Rémi Denis-Courmont > > This switches from custom instruction patterns to the regular large > memory model sequence with ADRP and LDR. In doing so, the ADD > instruction can be eliminated in the SDEI handler, and the code no > longer assumes that the trampoline vectors and the vectors address both > start on a page boundary. > > Signed-off-by: Rémi Denis-Courmont I queued the 3 trampoline patches for 5.7. Thanks. -- Catalin