From: Arnaldo Carvalho de Melo <arnaldo.melo@gmail.com>
To: "Hunter, Adrian" <adrian.hunter@intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>,
Masami Hiramatsu <mhiramat@kernel.org>,
Mingbo Zhang <whensungoes@gmail.com>,
"x86@kernel.org" <x86@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
"H. Peter Anvin" <hpa@zytor.com>, Andi Kleen <ak@linux.intel.com>,
Josh Poimboeuf <jpoimboe@redhat.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions
Date: Thu, 26 Mar 2020 11:57:26 -0300 [thread overview]
Message-ID: <20200326145726.GC6411@kernel.org> (raw)
In-Reply-To: <363DA0ED52042842948283D2FC38E4649C72EFF3@IRSMSX106.ger.corp.intel.com>
Em Thu, Mar 26, 2020 at 02:19:07PM +0000, Hunter, Adrian escreveu:
> > -----Original Message-----
> > From: Arnaldo Carvalho de Melo <acme@redhat.com>
> > Sent: Thursday, March 26, 2020 3:56 PM
> > To: Hunter, Adrian <adrian.hunter@intel.com>
> > Cc: Masami Hiramatsu <mhiramat@kernel.org>; Mingbo Zhang
> > <whensungoes@gmail.com>; Arnaldo Carvalho de Melo
> > <acme@kernel.org>; x86@kernel.org; Thomas Gleixner
> > <tglx@linutronix.de>; Ingo Molnar <mingo@redhat.com>; Borislav Petkov
> > <bp@alien8.de>; H. Peter Anvin <hpa@zytor.com>; Andi Kleen
> > <ak@linux.intel.com>; Josh Poimboeuf <jpoimboe@redhat.com>; linux-
> > kernel@vger.kernel.org
> > Subject: Re: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET
> > instructions
> >
> > Em Thu, Mar 26, 2020 at 07:09:45AM +0200, Adrian Hunter escreveu:
> > > On 26/03/20 3:31 am, Masami Hiramatsu wrote:
> > > > Hi,
> > > >
> > > > On Mon, 2 Mar 2020 23:50:30 -0500
> > > > Mingbo Zhang <whensungoes@gmail.com> wrote:
> > > >
> > > >> Intel CET instructions are not described in the Intel SDM. When
> > > >> trying to get the instruction length, the following instructions
> > > >> get wrong (missing ModR/M byte).
> > > >>
> > > >> RDSSPD r32
> > > >> RSDDPQ r64
> > > >> ENDBR32
> > > >> ENDBR64
> > > >> WRSSD r/m32, r32
> > > >> WRSSQ r/m64, r64
> > > >>
> > > >> RDSSPD/Q and ENDBR32/64 use the same opcode (f3 0f 1e) slot, which
> > > >> is described in SDM as Reserved-NOP with no encoding characters,
> > > >> and got an empty slot in the opcode map. WRSSD/Q (0f 38 f6) also got
> > an empty slot.
> > > >>
> > > >
> > > > This looks good to me. BTW, wouldn't we need to add decode test cases
> > to perf?
> > > >
> > > > Acked-by: Masami Hiramatsu <mhiramat@kernel.org>
> > > >
> > > > Thank you,
> > > >
> > >
> > > We have correct patches that you ack'ed for CET here:
> > >
> > >
> > > https://lore.kernel.org/lkml/20200204171425.28073-1-yu-cheng.yu@intel.
> > > com/
> > >
> > > But they have not yet been applied.
> > >
> > > Sorry for the confusion.
> >
> > I'll collect them, thanks for pointing this out.
>
> The patches are in tip courtesy of Borislav Petkov thank you!
Ok, thanks Borislav,
- Arnaldo
next prev parent reply other threads:[~2020-03-26 14:57 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-03 4:50 [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions Mingbo Zhang
2020-03-03 7:17 ` Adrian Hunter
2020-03-03 7:20 ` Adrian Hunter
2020-03-16 7:10 ` Adrian Hunter
2020-03-25 6:10 ` Adrian Hunter
2020-03-26 1:31 ` Masami Hiramatsu
2020-03-26 5:09 ` Adrian Hunter
2020-03-26 13:55 ` Arnaldo Carvalho de Melo
2020-03-26 14:19 ` Hunter, Adrian
2020-03-26 14:57 ` Arnaldo Carvalho de Melo [this message]
2020-03-26 15:01 ` Arnaldo Carvalho de Melo
2020-03-26 17:36 ` Adrian Hunter
2020-03-26 20:35 ` Arnaldo Carvalho de Melo
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