* [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions @ 2020-03-03 4:50 Mingbo Zhang 2020-03-03 7:17 ` Adrian Hunter 2020-03-26 1:31 ` Masami Hiramatsu 0 siblings, 2 replies; 13+ messages in thread From: Mingbo Zhang @ 2020-03-03 4:50 UTC (permalink / raw) To: x86 Cc: Mingbo Zhang, Thomas Gleixner, Ingo Molnar, Borislav Petkov, H. Peter Anvin, Masami Hiramatsu, Adrian Hunter, Arnaldo Carvalho de Melo, Andi Kleen, Josh Poimboeuf, linux-kernel Intel CET instructions are not described in the Intel SDM. When trying to get the instruction length, the following instructions get wrong (missing ModR/M byte). RDSSPD r32 RSDDPQ r64 ENDBR32 ENDBR64 WRSSD r/m32, r32 WRSSQ r/m64, r64 RDSSPD/Q and ENDBR32/64 use the same opcode (f3 0f 1e) slot, which is described in SDM as Reserved-NOP with no encoding characters, and got an empty slot in the opcode map. WRSSD/Q (0f 38 f6) also got an empty slot. Signed-off-by: Mingbo Zhang <whensungoes@gmail.com> --- arch/x86/lib/x86-opcode-map.txt | 4 ++-- tools/arch/x86/lib/x86-opcode-map.txt | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index 53adc1762ec0..0e3434c882d4 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -366,7 +366,7 @@ AVXcode: 1 1b: BNDCN Gv,Ev (F2) | BNDMOV Ev,Gv (66) | BNDMK Gv,Ev (F3) | BNDSTX Ev,Gv 1c: Grp20 (1A),(1C) 1d: -1e: +1e: NOP Gy,Gy 1f: NOP Ev # 0x0f 0x20-0x2f 20: MOV Rd,Cd @@ -804,7 +804,7 @@ f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2) | CRC32 Gd,Ew (66&F2) f2: ANDN Gy,By,Ey (v) f3: Grp17 (1A) f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v) -f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) +f6: NOP Ey,Gy | ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) | SHRX Gy,Ey,By (F2),(v) f8: MOVDIR64B Gv,Mdqq (66) | ENQCMD Gv,Mdqq (F2) | ENQCMDS Gv,Mdqq (F3) f9: MOVDIRI My,Gy diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86-opcode-map.txt index 53adc1762ec0..0e3434c882d4 100644 --- a/tools/arch/x86/lib/x86-opcode-map.txt +++ b/tools/arch/x86/lib/x86-opcode-map.txt @@ -366,7 +366,7 @@ AVXcode: 1 1b: BNDCN Gv,Ev (F2) | BNDMOV Ev,Gv (66) | BNDMK Gv,Ev (F3) | BNDSTX Ev,Gv 1c: Grp20 (1A),(1C) 1d: -1e: +1e: NOP Gy,Gy 1f: NOP Ev # 0x0f 0x20-0x2f 20: MOV Rd,Cd @@ -804,7 +804,7 @@ f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2) | CRC32 Gd,Ew (66&F2) f2: ANDN Gy,By,Ey (v) f3: Grp17 (1A) f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v) -f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) +f6: NOP Ey,Gy | ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) | SHRX Gy,Ey,By (F2),(v) f8: MOVDIR64B Gv,Mdqq (66) | ENQCMD Gv,Mdqq (F2) | ENQCMDS Gv,Mdqq (F3) f9: MOVDIRI My,Gy -- 2.25.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions 2020-03-03 4:50 [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions Mingbo Zhang @ 2020-03-03 7:17 ` Adrian Hunter 2020-03-03 7:20 ` Adrian Hunter 2020-03-16 7:10 ` Adrian Hunter 2020-03-26 1:31 ` Masami Hiramatsu 1 sibling, 2 replies; 13+ messages in thread From: Adrian Hunter @ 2020-03-03 7:17 UTC (permalink / raw) To: Mingbo Zhang, x86 Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, H. Peter Anvin, Masami Hiramatsu, Arnaldo Carvalho de Melo, Andi Kleen, Josh Poimboeuf, linux-kernel, Yu-cheng Yu On 3/03/20 6:50 am, Mingbo Zhang wrote: > Intel CET instructions are not described in the Intel SDM. When trying to > get the instruction length, the following instructions get wrong (missing > ModR/M byte). > > RDSSPD r32 > RSDDPQ r64 > ENDBR32 > ENDBR64 > WRSSD r/m32, r32 > WRSSQ r/m64, r64 > > RDSSPD/Q and ENDBR32/64 use the same opcode (f3 0f 1e) slot, which is > described in SDM as Reserved-NOP with no encoding characters, and got an > empty slot in the opcode map. WRSSD/Q (0f 38 f6) also got an empty slot. We have patches for that: https://lore.kernel.org/lkml/20200204171425.28073-1-yu-cheng.yu@intel.com/ But they have not yet been applied. Arnaldo, could you take them? ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions 2020-03-03 7:17 ` Adrian Hunter @ 2020-03-03 7:20 ` Adrian Hunter 2020-03-16 7:10 ` Adrian Hunter 1 sibling, 0 replies; 13+ messages in thread From: Adrian Hunter @ 2020-03-03 7:20 UTC (permalink / raw) To: Mingbo Zhang, x86 Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, H. Peter Anvin, Masami Hiramatsu, Arnaldo Carvalho de Melo, Andi Kleen, Josh Poimboeuf, linux-kernel, Yu-cheng Yu On 3/03/20 9:17 am, Adrian Hunter wrote: > On 3/03/20 6:50 am, Mingbo Zhang wrote: >> Intel CET instructions are not described in the Intel SDM. When trying to >> get the instruction length, the following instructions get wrong (missing >> ModR/M byte). >> >> RDSSPD r32 >> RSDDPQ r64 >> ENDBR32 >> ENDBR64 >> WRSSD r/m32, r32 >> WRSSQ r/m64, r64 >> >> RDSSPD/Q and ENDBR32/64 use the same opcode (f3 0f 1e) slot, which is >> described in SDM as Reserved-NOP with no encoding characters, and got an >> empty slot in the opcode map. WRSSD/Q (0f 38 f6) also got an empty slot. > > We have patches for that: > > https://lore.kernel.org/lkml/20200204171425.28073-1-yu-cheng.yu@intel.com/ > > But they have not yet been applied. Arnaldo, could you take them? > For reference: Subject: [PATCH 0/2] Introduce Control-flow Enforcement opcodes Date: Tue, 4 Feb 2020 09:14:23 -0800 Message-ID: <20200204171425.28073-1-yu-cheng.yu@intel.com> (raw) Control-flow Enforcement (CET) introduces 10 new instructions [1]. Add them to the opcode map. This series has been separated from the CET patches [2] for ease of review. [1] Detailed information on CET can be found in "Intel 64 and IA-32 Architectures Software Developer's Manual": https://software.intel.com/en-us/download/intel-64-and-ia-32- architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4 [2] CET patches: https://lkml.kernel.org/r/20190813205225.12032-1-yu-cheng.yu@intel.com/ https://lkml.kernel.org/r/20190813205359.12196-1-yu-cheng.yu@intel.com/ Adrian Hunter (1): x86/insn: perf tools: Add CET instructions to the new instructions test Yu-cheng Yu (1): x86/insn: Add Control-flow Enforcement (CET) instructions to the opcode map arch/x86/lib/x86-opcode-map.txt | 17 +- tools/arch/x86/lib/x86-opcode-map.txt | 17 +- tools/perf/arch/x86/tests/insn-x86-dat-32.c | 112 +++++++++ tools/perf/arch/x86/tests/insn-x86-dat-64.c | 196 +++++++++++++++ tools/perf/arch/x86/tests/insn-x86-dat-src.c | 236 +++++++++++++++++++ 5 files changed, 566 insertions(+), 12 deletions(-) ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions 2020-03-03 7:17 ` Adrian Hunter 2020-03-03 7:20 ` Adrian Hunter @ 2020-03-16 7:10 ` Adrian Hunter 2020-03-25 6:10 ` Adrian Hunter 1 sibling, 1 reply; 13+ messages in thread From: Adrian Hunter @ 2020-03-16 7:10 UTC (permalink / raw) To: Mingbo Zhang, x86 Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, H. Peter Anvin, Masami Hiramatsu, Arnaldo Carvalho de Melo, Andi Kleen, Josh Poimboeuf, linux-kernel, Yu-cheng Yu, Jiri Olsa On 3/03/20 9:17 am, Adrian Hunter wrote: > On 3/03/20 6:50 am, Mingbo Zhang wrote: >> Intel CET instructions are not described in the Intel SDM. When trying to >> get the instruction length, the following instructions get wrong (missing >> ModR/M byte). >> >> RDSSPD r32 >> RSDDPQ r64 >> ENDBR32 >> ENDBR64 >> WRSSD r/m32, r32 >> WRSSQ r/m64, r64 >> >> RDSSPD/Q and ENDBR32/64 use the same opcode (f3 0f 1e) slot, which is >> described in SDM as Reserved-NOP with no encoding characters, and got an >> empty slot in the opcode map. WRSSD/Q (0f 38 f6) also got an empty slot. > > We have patches for that: > > https://lore.kernel.org/lkml/20200204171425.28073-1-yu-cheng.yu@intel.com/ > > But they have not yet been applied. Arnaldo, could you take them? > Any takers? ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions 2020-03-16 7:10 ` Adrian Hunter @ 2020-03-25 6:10 ` Adrian Hunter 0 siblings, 0 replies; 13+ messages in thread From: Adrian Hunter @ 2020-03-25 6:10 UTC (permalink / raw) To: Mingbo Zhang, x86 Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, H. Peter Anvin, Masami Hiramatsu, Arnaldo Carvalho de Melo, Andi Kleen, Josh Poimboeuf, linux-kernel, Yu-cheng Yu, Jiri Olsa On 16/03/20 9:10 am, Adrian Hunter wrote: > On 3/03/20 9:17 am, Adrian Hunter wrote: >> On 3/03/20 6:50 am, Mingbo Zhang wrote: >>> Intel CET instructions are not described in the Intel SDM. When trying to >>> get the instruction length, the following instructions get wrong (missing >>> ModR/M byte). >>> >>> RDSSPD r32 >>> RSDDPQ r64 >>> ENDBR32 >>> ENDBR64 >>> WRSSD r/m32, r32 >>> WRSSQ r/m64, r64 >>> >>> RDSSPD/Q and ENDBR32/64 use the same opcode (f3 0f 1e) slot, which is >>> described in SDM as Reserved-NOP with no encoding characters, and got an >>> empty slot in the opcode map. WRSSD/Q (0f 38 f6) also got an empty slot. >> >> We have patches for that: >> >> https://lore.kernel.org/lkml/20200204171425.28073-1-yu-cheng.yu@intel.com/ >> >> But they have not yet been applied. Arnaldo, could you take them? >> > > Any takers? > :-) ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions 2020-03-03 4:50 [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions Mingbo Zhang 2020-03-03 7:17 ` Adrian Hunter @ 2020-03-26 1:31 ` Masami Hiramatsu 2020-03-26 5:09 ` Adrian Hunter 1 sibling, 1 reply; 13+ messages in thread From: Masami Hiramatsu @ 2020-03-26 1:31 UTC (permalink / raw) To: Mingbo Zhang, Arnaldo Carvalho de Melo Cc: x86, Thomas Gleixner, Ingo Molnar, Borislav Petkov, H. Peter Anvin, Masami Hiramatsu, Adrian Hunter, Arnaldo Carvalho de Melo, Andi Kleen, Josh Poimboeuf, linux-kernel Hi, On Mon, 2 Mar 2020 23:50:30 -0500 Mingbo Zhang <whensungoes@gmail.com> wrote: > Intel CET instructions are not described in the Intel SDM. When trying to > get the instruction length, the following instructions get wrong (missing > ModR/M byte). > > RDSSPD r32 > RSDDPQ r64 > ENDBR32 > ENDBR64 > WRSSD r/m32, r32 > WRSSQ r/m64, r64 > > RDSSPD/Q and ENDBR32/64 use the same opcode (f3 0f 1e) slot, which is > described in SDM as Reserved-NOP with no encoding characters, and got an > empty slot in the opcode map. WRSSD/Q (0f 38 f6) also got an empty slot. > This looks good to me. BTW, wouldn't we need to add decode test cases to perf? Acked-by: Masami Hiramatsu <mhiramat@kernel.org> Thank you, > Signed-off-by: Mingbo Zhang <whensungoes@gmail.com> > --- > arch/x86/lib/x86-opcode-map.txt | 4 ++-- > tools/arch/x86/lib/x86-opcode-map.txt | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt > index 53adc1762ec0..0e3434c882d4 100644 > --- a/arch/x86/lib/x86-opcode-map.txt > +++ b/arch/x86/lib/x86-opcode-map.txt > @@ -366,7 +366,7 @@ AVXcode: 1 > 1b: BNDCN Gv,Ev (F2) | BNDMOV Ev,Gv (66) | BNDMK Gv,Ev (F3) | BNDSTX Ev,Gv > 1c: Grp20 (1A),(1C) > 1d: > -1e: > +1e: NOP Gy,Gy > 1f: NOP Ev > # 0x0f 0x20-0x2f > 20: MOV Rd,Cd > @@ -804,7 +804,7 @@ f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2) | CRC32 Gd,Ew (66&F2) > f2: ANDN Gy,By,Ey (v) > f3: Grp17 (1A) > f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v) > -f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) > +f6: NOP Ey,Gy | ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) > f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) | SHRX Gy,Ey,By (F2),(v) > f8: MOVDIR64B Gv,Mdqq (66) | ENQCMD Gv,Mdqq (F2) | ENQCMDS Gv,Mdqq (F3) > f9: MOVDIRI My,Gy > diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86-opcode-map.txt > index 53adc1762ec0..0e3434c882d4 100644 > --- a/tools/arch/x86/lib/x86-opcode-map.txt > +++ b/tools/arch/x86/lib/x86-opcode-map.txt > @@ -366,7 +366,7 @@ AVXcode: 1 > 1b: BNDCN Gv,Ev (F2) | BNDMOV Ev,Gv (66) | BNDMK Gv,Ev (F3) | BNDSTX Ev,Gv > 1c: Grp20 (1A),(1C) > 1d: > -1e: > +1e: NOP Gy,Gy > 1f: NOP Ev > # 0x0f 0x20-0x2f > 20: MOV Rd,Cd > @@ -804,7 +804,7 @@ f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2) | CRC32 Gd,Ew (66&F2) > f2: ANDN Gy,By,Ey (v) > f3: Grp17 (1A) > f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v) > -f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) > +f6: NOP Ey,Gy | ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) > f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) | SHRX Gy,Ey,By (F2),(v) > f8: MOVDIR64B Gv,Mdqq (66) | ENQCMD Gv,Mdqq (F2) | ENQCMDS Gv,Mdqq (F3) > f9: MOVDIRI My,Gy > -- > 2.25.1 > -- Masami Hiramatsu <mhiramat@kernel.org> ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions 2020-03-26 1:31 ` Masami Hiramatsu @ 2020-03-26 5:09 ` Adrian Hunter 2020-03-26 13:55 ` Arnaldo Carvalho de Melo 0 siblings, 1 reply; 13+ messages in thread From: Adrian Hunter @ 2020-03-26 5:09 UTC (permalink / raw) To: Masami Hiramatsu, Mingbo Zhang, Arnaldo Carvalho de Melo Cc: x86, Thomas Gleixner, Ingo Molnar, Borislav Petkov, H. Peter Anvin, Arnaldo Carvalho de Melo, Andi Kleen, Josh Poimboeuf, linux-kernel On 26/03/20 3:31 am, Masami Hiramatsu wrote: > Hi, > > On Mon, 2 Mar 2020 23:50:30 -0500 > Mingbo Zhang <whensungoes@gmail.com> wrote: > >> Intel CET instructions are not described in the Intel SDM. When trying to >> get the instruction length, the following instructions get wrong (missing >> ModR/M byte). >> >> RDSSPD r32 >> RSDDPQ r64 >> ENDBR32 >> ENDBR64 >> WRSSD r/m32, r32 >> WRSSQ r/m64, r64 >> >> RDSSPD/Q and ENDBR32/64 use the same opcode (f3 0f 1e) slot, which is >> described in SDM as Reserved-NOP with no encoding characters, and got an >> empty slot in the opcode map. WRSSD/Q (0f 38 f6) also got an empty slot. >> > > This looks good to me. BTW, wouldn't we need to add decode test cases to perf? > > Acked-by: Masami Hiramatsu <mhiramat@kernel.org> > > Thank you, > We have correct patches that you ack'ed for CET here: https://lore.kernel.org/lkml/20200204171425.28073-1-yu-cheng.yu@intel.com/ But they have not yet been applied. Sorry for the confusion. ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions 2020-03-26 5:09 ` Adrian Hunter @ 2020-03-26 13:55 ` Arnaldo Carvalho de Melo 2020-03-26 14:19 ` Hunter, Adrian 0 siblings, 1 reply; 13+ messages in thread From: Arnaldo Carvalho de Melo @ 2020-03-26 13:55 UTC (permalink / raw) To: Adrian Hunter Cc: Masami Hiramatsu, Mingbo Zhang, Arnaldo Carvalho de Melo, x86, Thomas Gleixner, Ingo Molnar, Borislav Petkov, H. Peter Anvin, Andi Kleen, Josh Poimboeuf, linux-kernel Em Thu, Mar 26, 2020 at 07:09:45AM +0200, Adrian Hunter escreveu: > On 26/03/20 3:31 am, Masami Hiramatsu wrote: > > Hi, > > > > On Mon, 2 Mar 2020 23:50:30 -0500 > > Mingbo Zhang <whensungoes@gmail.com> wrote: > > > >> Intel CET instructions are not described in the Intel SDM. When trying to > >> get the instruction length, the following instructions get wrong (missing > >> ModR/M byte). > >> > >> RDSSPD r32 > >> RSDDPQ r64 > >> ENDBR32 > >> ENDBR64 > >> WRSSD r/m32, r32 > >> WRSSQ r/m64, r64 > >> > >> RDSSPD/Q and ENDBR32/64 use the same opcode (f3 0f 1e) slot, which is > >> described in SDM as Reserved-NOP with no encoding characters, and got an > >> empty slot in the opcode map. WRSSD/Q (0f 38 f6) also got an empty slot. > >> > > > > This looks good to me. BTW, wouldn't we need to add decode test cases to perf? > > > > Acked-by: Masami Hiramatsu <mhiramat@kernel.org> > > > > Thank you, > > > > We have correct patches that you ack'ed for CET here: > > https://lore.kernel.org/lkml/20200204171425.28073-1-yu-cheng.yu@intel.com/ > > But they have not yet been applied. > > Sorry for the confusion. I'll collect them, thanks for pointing this out. - Arnaldo ^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions 2020-03-26 13:55 ` Arnaldo Carvalho de Melo @ 2020-03-26 14:19 ` Hunter, Adrian 2020-03-26 14:57 ` Arnaldo Carvalho de Melo 0 siblings, 1 reply; 13+ messages in thread From: Hunter, Adrian @ 2020-03-26 14:19 UTC (permalink / raw) To: Arnaldo Carvalho de Melo Cc: Masami Hiramatsu, Mingbo Zhang, Arnaldo Carvalho de Melo, x86@kernel.org, Thomas Gleixner, Ingo Molnar, Borislav Petkov, H. Peter Anvin, Andi Kleen, Josh Poimboeuf, linux-kernel@vger.kernel.org > -----Original Message----- > From: Arnaldo Carvalho de Melo <acme@redhat.com> > Sent: Thursday, March 26, 2020 3:56 PM > To: Hunter, Adrian <adrian.hunter@intel.com> > Cc: Masami Hiramatsu <mhiramat@kernel.org>; Mingbo Zhang > <whensungoes@gmail.com>; Arnaldo Carvalho de Melo > <acme@kernel.org>; x86@kernel.org; Thomas Gleixner > <tglx@linutronix.de>; Ingo Molnar <mingo@redhat.com>; Borislav Petkov > <bp@alien8.de>; H. Peter Anvin <hpa@zytor.com>; Andi Kleen > <ak@linux.intel.com>; Josh Poimboeuf <jpoimboe@redhat.com>; linux- > kernel@vger.kernel.org > Subject: Re: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET > instructions > > Em Thu, Mar 26, 2020 at 07:09:45AM +0200, Adrian Hunter escreveu: > > On 26/03/20 3:31 am, Masami Hiramatsu wrote: > > > Hi, > > > > > > On Mon, 2 Mar 2020 23:50:30 -0500 > > > Mingbo Zhang <whensungoes@gmail.com> wrote: > > > > > >> Intel CET instructions are not described in the Intel SDM. When > > >> trying to get the instruction length, the following instructions > > >> get wrong (missing ModR/M byte). > > >> > > >> RDSSPD r32 > > >> RSDDPQ r64 > > >> ENDBR32 > > >> ENDBR64 > > >> WRSSD r/m32, r32 > > >> WRSSQ r/m64, r64 > > >> > > >> RDSSPD/Q and ENDBR32/64 use the same opcode (f3 0f 1e) slot, which > > >> is described in SDM as Reserved-NOP with no encoding characters, > > >> and got an empty slot in the opcode map. WRSSD/Q (0f 38 f6) also got > an empty slot. > > >> > > > > > > This looks good to me. BTW, wouldn't we need to add decode test cases > to perf? > > > > > > Acked-by: Masami Hiramatsu <mhiramat@kernel.org> > > > > > > Thank you, > > > > > > > We have correct patches that you ack'ed for CET here: > > > > > > https://lore.kernel.org/lkml/20200204171425.28073-1-yu-cheng.yu@intel. > > com/ > > > > But they have not yet been applied. > > > > Sorry for the confusion. > > I'll collect them, thanks for pointing this out. The patches are in tip courtesy of Borislav Petkov thank you! ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions 2020-03-26 14:19 ` Hunter, Adrian @ 2020-03-26 14:57 ` Arnaldo Carvalho de Melo 2020-03-26 15:01 ` Arnaldo Carvalho de Melo 0 siblings, 1 reply; 13+ messages in thread From: Arnaldo Carvalho de Melo @ 2020-03-26 14:57 UTC (permalink / raw) To: Hunter, Adrian Cc: Arnaldo Carvalho de Melo, Masami Hiramatsu, Mingbo Zhang, x86@kernel.org, Thomas Gleixner, Ingo Molnar, Borislav Petkov, H. Peter Anvin, Andi Kleen, Josh Poimboeuf, linux-kernel@vger.kernel.org Em Thu, Mar 26, 2020 at 02:19:07PM +0000, Hunter, Adrian escreveu: > > -----Original Message----- > > From: Arnaldo Carvalho de Melo <acme@redhat.com> > > Sent: Thursday, March 26, 2020 3:56 PM > > To: Hunter, Adrian <adrian.hunter@intel.com> > > Cc: Masami Hiramatsu <mhiramat@kernel.org>; Mingbo Zhang > > <whensungoes@gmail.com>; Arnaldo Carvalho de Melo > > <acme@kernel.org>; x86@kernel.org; Thomas Gleixner > > <tglx@linutronix.de>; Ingo Molnar <mingo@redhat.com>; Borislav Petkov > > <bp@alien8.de>; H. Peter Anvin <hpa@zytor.com>; Andi Kleen > > <ak@linux.intel.com>; Josh Poimboeuf <jpoimboe@redhat.com>; linux- > > kernel@vger.kernel.org > > Subject: Re: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET > > instructions > > > > Em Thu, Mar 26, 2020 at 07:09:45AM +0200, Adrian Hunter escreveu: > > > On 26/03/20 3:31 am, Masami Hiramatsu wrote: > > > > Hi, > > > > > > > > On Mon, 2 Mar 2020 23:50:30 -0500 > > > > Mingbo Zhang <whensungoes@gmail.com> wrote: > > > > > > > >> Intel CET instructions are not described in the Intel SDM. When > > > >> trying to get the instruction length, the following instructions > > > >> get wrong (missing ModR/M byte). > > > >> > > > >> RDSSPD r32 > > > >> RSDDPQ r64 > > > >> ENDBR32 > > > >> ENDBR64 > > > >> WRSSD r/m32, r32 > > > >> WRSSQ r/m64, r64 > > > >> > > > >> RDSSPD/Q and ENDBR32/64 use the same opcode (f3 0f 1e) slot, which > > > >> is described in SDM as Reserved-NOP with no encoding characters, > > > >> and got an empty slot in the opcode map. WRSSD/Q (0f 38 f6) also got > > an empty slot. > > > >> > > > > > > > > This looks good to me. BTW, wouldn't we need to add decode test cases > > to perf? > > > > > > > > Acked-by: Masami Hiramatsu <mhiramat@kernel.org> > > > > > > > > Thank you, > > > > > > > > > > We have correct patches that you ack'ed for CET here: > > > > > > > > > https://lore.kernel.org/lkml/20200204171425.28073-1-yu-cheng.yu@intel. > > > com/ > > > > > > But they have not yet been applied. > > > > > > Sorry for the confusion. > > > > I'll collect them, thanks for pointing this out. > > The patches are in tip courtesy of Borislav Petkov thank you! Ok, thanks Borislav, - Arnaldo ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions 2020-03-26 14:57 ` Arnaldo Carvalho de Melo @ 2020-03-26 15:01 ` Arnaldo Carvalho de Melo 2020-03-26 17:36 ` Adrian Hunter 0 siblings, 1 reply; 13+ messages in thread From: Arnaldo Carvalho de Melo @ 2020-03-26 15:01 UTC (permalink / raw) To: Hunter, Adrian Cc: Arnaldo Carvalho de Melo, Masami Hiramatsu, Mingbo Zhang, x86@kernel.org, Thomas Gleixner, Ingo Molnar, Borislav Petkov, H. Peter Anvin, Andi Kleen, Josh Poimboeuf, linux-kernel@vger.kernel.org Em Thu, Mar 26, 2020 at 11:57:26AM -0300, Arnaldo Carvalho de Melo escreveu: > Em Thu, Mar 26, 2020 at 02:19:07PM +0000, Hunter, Adrian escreveu: > > > > But they have not yet been applied. > > > > Sorry for the confusion. > > > I'll collect them, thanks for pointing this out. > > The patches are in tip courtesy of Borislav Petkov thank you! > Ok, thanks Borislav, I didn't notice because it didn't made into tip/perf/core :-\ In what branch is it btw, I couldn't find any cset with substr summary "Add Control-flow Enforcement" in, tip/master also doesn't have it. - Arnaldo ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions 2020-03-26 15:01 ` Arnaldo Carvalho de Melo @ 2020-03-26 17:36 ` Adrian Hunter 2020-03-26 20:35 ` Arnaldo Carvalho de Melo 0 siblings, 1 reply; 13+ messages in thread From: Adrian Hunter @ 2020-03-26 17:36 UTC (permalink / raw) To: Arnaldo Carvalho de Melo Cc: Arnaldo Carvalho de Melo, Masami Hiramatsu, Mingbo Zhang, x86@kernel.org, Thomas Gleixner, Ingo Molnar, Borislav Petkov, H. Peter Anvin, Andi Kleen, Josh Poimboeuf, linux-kernel@vger.kernel.org On 26/03/20 5:01 pm, Arnaldo Carvalho de Melo wrote: > Em Thu, Mar 26, 2020 at 11:57:26AM -0300, Arnaldo Carvalho de Melo escreveu: >> Em Thu, Mar 26, 2020 at 02:19:07PM +0000, Hunter, Adrian escreveu: >>>>> But they have not yet been applied. > >>>>> Sorry for the confusion. > >>>> I'll collect them, thanks for pointing this out. > >>> The patches are in tip courtesy of Borislav Petkov thank you! > >> Ok, thanks Borislav, > > I didn't notice because it didn't made into tip/perf/core :-\ In what > branch is it btw, I couldn't find any cset with substr summary "Add > Control-flow Enforcement" in, tip/master also doesn't have it. > > - Arnaldo > x86/misc ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions 2020-03-26 17:36 ` Adrian Hunter @ 2020-03-26 20:35 ` Arnaldo Carvalho de Melo 0 siblings, 0 replies; 13+ messages in thread From: Arnaldo Carvalho de Melo @ 2020-03-26 20:35 UTC (permalink / raw) To: Adrian Hunter Cc: Masami Hiramatsu, Mingbo Zhang, x86@kernel.org, Thomas Gleixner, Ingo Molnar, Borislav Petkov, H. Peter Anvin, Andi Kleen, Josh Poimboeuf, linux-kernel@vger.kernel.org Em Thu, Mar 26, 2020 at 07:36:27PM +0200, Adrian Hunter escreveu: > On 26/03/20 5:01 pm, Arnaldo Carvalho de Melo wrote: > > Em Thu, Mar 26, 2020 at 11:57:26AM -0300, Arnaldo Carvalho de Melo escreveu: > >> Em Thu, Mar 26, 2020 at 02:19:07PM +0000, Hunter, Adrian escreveu: > >>>>> But they have not yet been applied. > > > >>>>> Sorry for the confusion. > > > >>>> I'll collect them, thanks for pointing this out. > > > >>> The patches are in tip courtesy of Borislav Petkov thank you! > > > >> Ok, thanks Borislav, > > > > I didn't notice because it didn't made into tip/perf/core :-\ In what > > branch is it btw, I couldn't find any cset with substr summary "Add > > Control-flow Enforcement" in, tip/master also doesn't have it. > > > > - Arnaldo > > > > > x86/misc Right, he told me, thanks, - Arnaldo ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2020-03-26 20:36 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-03-03 4:50 [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions Mingbo Zhang 2020-03-03 7:17 ` Adrian Hunter 2020-03-03 7:20 ` Adrian Hunter 2020-03-16 7:10 ` Adrian Hunter 2020-03-25 6:10 ` Adrian Hunter 2020-03-26 1:31 ` Masami Hiramatsu 2020-03-26 5:09 ` Adrian Hunter 2020-03-26 13:55 ` Arnaldo Carvalho de Melo 2020-03-26 14:19 ` Hunter, Adrian 2020-03-26 14:57 ` Arnaldo Carvalho de Melo 2020-03-26 15:01 ` Arnaldo Carvalho de Melo 2020-03-26 17:36 ` Adrian Hunter 2020-03-26 20:35 ` Arnaldo Carvalho de Melo
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