From: Sean Christopherson <sean.j.christopherson@intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
Junaid Shahid <junaids@google.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>
Subject: Re: [PATCH 3/3] KVM: x86: Sync SPTEs when injecting page/EPT fault into L1
Date: Sat, 28 Mar 2020 11:29:51 -0700 [thread overview]
Message-ID: <20200328182951.GR8104@linux.intel.com> (raw)
In-Reply-To: <20200326093516.24215-4-pbonzini@redhat.com>
On Thu, Mar 26, 2020 at 05:35:16AM -0400, Paolo Bonzini wrote:
> From: Junaid Shahid <junaids@google.com>
>
> When injecting a page fault or EPT violation/misconfiguration, KVM is
> not syncing any shadow PTEs associated with the faulting address,
> including those in previous MMUs that are associated with L1's current
> EPTP (in a nested EPT scenario), nor is it flushing any hardware TLB
> entries. All this is done by kvm_mmu_invalidate_gva.
>
> Page faults that are either !PRESENT or RSVD are exempt from the flushing,
> as the CPU is not allowed to cache such translations.
>
> Signed-off-by: Junaid Shahid <junaids@google.com>
> Co-developed-by: Sean Christopherson <sean.j.christopherson@intel.com>
> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
> Message-Id: <20200320212833.3507-8-sean.j.christopherson@intel.com>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> arch/x86/kvm/vmx/nested.c | 12 ++++++------
> arch/x86/kvm/vmx/vmx.c | 2 +-
> arch/x86/kvm/x86.c | 11 ++++++++++-
> 3 files changed, 17 insertions(+), 8 deletions(-)
>
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 522905523bf0..dbca6c3bd0db 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -618,8 +618,17 @@ bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
> WARN_ON_ONCE(fault->vector != PF_VECTOR);
>
> fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : vcpu->arch.walk_mmu;
> - fault_mmu->inject_page_fault(vcpu, fault);
>
> + /*
> + * Invalidate the TLB entry for the faulting address, if it exists,
> + * else the access will fault indefinitely (and to emulate hardware).
> + */
> + if ((fault->error_code & PFERR_PRESENT_MASK)
> + && !(fault->error_code & PFERR_RSVD_MASK))
What kind of heathen puts && on the new line? :-D
> + kvm_mmu_invalidate_gva(vcpu, fault_mmu,
> + fault->address, fault_mmu->root_hpa);
Another nit, why have the new line after fault_mmu? I.e.
kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
fault_mmu->root_hpa);
> +
> + fault_mmu->inject_page_fault(vcpu, fault);
> return fault->nested_page_fault;
> }
> EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
> --
> 2.18.2
>
prev parent reply other threads:[~2020-03-28 18:29 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-26 9:35 [PATCH 0/3] KVM: x86: sync SPTEs on page/EPT fault injection Paolo Bonzini
2020-03-26 9:35 ` [PATCH 1/3] KVM: x86: introduce kvm_mmu_invalidate_gva Paolo Bonzini
2020-03-28 18:26 ` Sean Christopherson
2020-03-30 10:45 ` Paolo Bonzini
2020-03-30 18:47 ` Sean Christopherson
2020-03-31 10:33 ` Vitaly Kuznetsov
2020-03-31 12:16 ` Paolo Bonzini
2020-03-26 9:35 ` [PATCH 2/3] KVM: x86: cleanup kvm_inject_emulated_page_fault Paolo Bonzini
2020-03-26 13:41 ` Vitaly Kuznetsov
2020-03-26 19:45 ` Paolo Bonzini
2020-03-27 12:48 ` Vitaly Kuznetsov
2020-03-28 18:41 ` Sean Christopherson
2020-03-26 9:35 ` [PATCH 3/3] KVM: x86: Sync SPTEs when injecting page/EPT fault into L1 Paolo Bonzini
2020-03-28 18:29 ` Sean Christopherson [this message]
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