public inbox for linux-kernel@vger.kernel.org
 help / color / mirror / Atom feed
From: Dmitry Osipenko <digetx@gmail.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
	"Jonathan Hunter" <jonathanh@nvidia.com>,
	"Artur Świgoń" <a.swigon@samsung.com>,
	"Georgi Djakov" <georgi.djakov@linaro.org>,
	"Rob Herring" <robh+dt@kernel.org>
Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	devicetree@vger.kernel.org
Subject: [PATCH v2 11/22] memory: tegra: Register as interconnect provider
Date: Mon, 30 Mar 2020 04:08:53 +0300	[thread overview]
Message-ID: <20200330010904.27643-12-digetx@gmail.com> (raw)
In-Reply-To: <20200330010904.27643-1-digetx@gmail.com>

Now memory controller is a memory interconnection provider. This allows us
to use interconnect API in order to change memory configuration.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/memory/tegra/mc.c | 118 ++++++++++++++++++++++++++++++++++++++
 drivers/memory/tegra/mc.h |   8 +++
 include/soc/tegra/mc.h    |   3 +
 3 files changed, 129 insertions(+)

diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index ec8403557ed4..bcf0478c5f5a 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -591,6 +591,117 @@ static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
+static int tegra_mc_icc_set(struct icc_node *src, struct icc_node *dst)
+{
+	return 0;
+}
+
+static int tegra_mc_icc_aggregate(struct icc_node *node,
+				  u32 tag, u32 avg_bw, u32 peak_bw,
+				  u32 *agg_avg, u32 *agg_peak)
+{
+	*agg_avg = min((u64)avg_bw + (*agg_avg), (u64)U32_MAX);
+	*agg_peak = max(*agg_peak, peak_bw);
+
+	return 0;
+}
+
+/*
+ * Memory Controller (MC) has few Memory Clients that are issuing memory
+ * bandwidth allocation requests to the MC interconnect provider. The MC
+ * provider aggregates the requests and then sends the aggregated request
+ * up to the External Memory Controller (EMC) interconnect provider which
+ * re-configures hardware interface to External Memory (EMEM) in accordance
+ * to the required bandwidth. Each MC interconnect node represents an
+ * individual Memory Client.
+ *
+ * Memory interconnect topology:
+ *
+ *               +----+
+ * +--------+    |    |
+ * | TEXSRD +--->+    |
+ * +--------+    |    |
+ *               |    |    +-----+    +------+
+ *    ...        | MC +--->+ EMC +--->+ EMEM |
+ *               |    |    +-----+    +------+
+ * +--------+    |    |
+ * | DISP.. +--->+    |
+ * +--------+    |    |
+ *               +----+
+ */
+static int tegra_mc_interconnect_setup(struct tegra_mc *mc)
+{
+	struct icc_onecell_data *data;
+	struct icc_node *node;
+	unsigned int num_nodes;
+	unsigned int i;
+	int err;
+
+	/* older device-trees don't have interconnect properties */
+	if (!of_find_property(mc->dev->of_node, "#interconnect-cells", NULL))
+		return 0;
+
+	num_nodes = mc->soc->num_clients;
+
+	data = devm_kzalloc(mc->dev, struct_size(data, nodes, num_nodes),
+			    GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	mc->provider.dev = mc->dev;
+	mc->provider.set = tegra_mc_icc_set;
+	mc->provider.data = data;
+	mc->provider.xlate = of_icc_xlate_onecell;
+	mc->provider.aggregate = tegra_mc_icc_aggregate;
+
+	err = icc_provider_add(&mc->provider);
+	if (err)
+		return err;
+
+	/* create Memory Controller node */
+	node = icc_node_create(TEGRA_ICC_MC);
+	err = PTR_ERR_OR_ZERO(node);
+	if (err)
+		goto del_provider;
+
+	node->name = "Memory Controller";
+	icc_node_add(node, &mc->provider);
+
+	/* link Memory Controller to External Memory Controller */
+	err = icc_link_create(node, TEGRA_ICC_EMC);
+	if (err)
+		goto remove_nodes;
+
+	for (i = 0; i < num_nodes; i++) {
+		/* create MC client node */
+		node = icc_node_create(mc->soc->clients[i].id);
+		err = PTR_ERR_OR_ZERO(node);
+		if (err)
+			goto remove_nodes;
+
+		node->name = mc->soc->clients[i].name;
+		icc_node_add(node, &mc->provider);
+
+		/* link Memory Client to Memory Controller */
+		err = icc_link_create(node, TEGRA_ICC_MC);
+		if (err)
+			goto remove_nodes;
+
+		data->nodes[i] = node;
+	}
+	data->num_nodes = num_nodes;
+
+	return 0;
+
+remove_nodes:
+	icc_nodes_remove(&mc->provider);
+
+del_provider:
+	icc_provider_del(&mc->provider);
+
+	return err;
+}
+
 static int tegra_mc_probe(struct platform_device *pdev)
 {
 	struct resource *res;
@@ -699,6 +810,13 @@ static int tegra_mc_probe(struct platform_device *pdev)
 		}
 	}
 
+	if (IS_ENABLED(CONFIG_INTERCONNECT)) {
+		err = tegra_mc_interconnect_setup(mc);
+		if (err)
+			dev_err(&pdev->dev, "failed to initialize ICC: %d\n",
+				err);
+	}
+
 	return 0;
 }
 
diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h
index 957c6eb74ff9..bb13747cd96c 100644
--- a/drivers/memory/tegra/mc.h
+++ b/drivers/memory/tegra/mc.h
@@ -114,4 +114,12 @@ extern const struct tegra_mc_soc tegra132_mc_soc;
 extern const struct tegra_mc_soc tegra210_mc_soc;
 #endif
 
+/*
+ * These IDs are for internal use of Tegra's ICC, the values are chosen
+ * such that they don't conflict with the device-tree ICC node IDs.
+ */
+#define TEGRA_ICC_EMC		1000
+#define TEGRA_ICC_EMEM		2000
+#define TEGRA_ICC_MC		3000
+
 #endif /* MEMORY_TEGRA_MC_H */
diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h
index 1238e35653d1..71de023f9f47 100644
--- a/include/soc/tegra/mc.h
+++ b/include/soc/tegra/mc.h
@@ -7,6 +7,7 @@
 #define __SOC_TEGRA_MC_H__
 
 #include <linux/err.h>
+#include <linux/interconnect-provider.h>
 #include <linux/reset-controller.h>
 #include <linux/types.h>
 
@@ -178,6 +179,8 @@ struct tegra_mc {
 
 	struct reset_controller_dev reset;
 
+	struct icc_provider provider;
+
 	spinlock_t lock;
 };
 
-- 
2.25.1


  parent reply	other threads:[~2020-03-30  1:10 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-30  1:08 [PATCH v2 00/22] Introduce memory interconnect for NVIDIA Tegra SoCs Dmitry Osipenko
2020-03-30  1:08 ` [PATCH v2 01/22] dt-bindings: memory: tegra20: mc: Document new interconnect property Dmitry Osipenko
2020-04-10 17:05   ` Rob Herring
2020-03-30  1:08 ` [PATCH v2 02/22] dt-bindings: memory: tegra20: emc: " Dmitry Osipenko
2020-04-10 17:06   ` Rob Herring
2020-03-30  1:08 ` [PATCH v2 03/22] dt-bindings: memory: tegra30: mc: " Dmitry Osipenko
2020-04-10 17:06   ` Rob Herring
2020-03-30  1:08 ` [PATCH v2 04/22] dt-bindings: memory: tegra30: emc: " Dmitry Osipenko
2020-04-10 17:07   ` Rob Herring
2020-03-30  1:08 ` [PATCH v2 05/22] dt-bindings: host1x: Document new interconnect properties Dmitry Osipenko
2020-04-10 17:09   ` Rob Herring
2020-04-10 18:28     ` Dmitry Osipenko
2020-03-30  1:08 ` [PATCH v2 06/22] dt-bindings: memory: tegra20: Add memory client IDs Dmitry Osipenko
2020-04-10 17:10   ` Rob Herring
2020-03-30  1:08 ` [PATCH v2 07/22] dt-bindings: memory: tegra30: " Dmitry Osipenko
2020-04-10 17:10   ` Rob Herring
2020-03-30  1:08 ` [PATCH v2 08/22] ARM: tegra: Add interconnect properties to Tegra20 device-tree Dmitry Osipenko
2020-03-30  1:08 ` [PATCH v2 09/22] ARM: tegra: Add interconnect properties to Tegra30 device-tree Dmitry Osipenko
2020-03-30  1:08 ` [PATCH v2 10/22] interconnect: Relax requirement in of_icc_get_from_provider() Dmitry Osipenko
2020-03-30  1:08 ` Dmitry Osipenko [this message]
2020-04-13 12:43   ` [PATCH v2 11/22] memory: tegra: Register as interconnect provider Georgi Djakov
2020-04-13 15:01     ` Dmitry Osipenko
2020-03-30  1:08 ` [PATCH v2 12/22] memory: tegra20-emc: Use devm_platform_ioremap_resource Dmitry Osipenko
2020-03-30  1:08 ` [PATCH v2 13/22] memory: tegra20-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko
2020-03-30  1:08 ` [PATCH v2 14/22] memory: tegra20-emc: Register as interconnect provider Dmitry Osipenko
2020-03-30  1:08 ` [PATCH v2 15/22] memory: tegra20-emc: Create tegra20-devfreq device Dmitry Osipenko
2020-03-30  1:08 ` [PATCH v2 16/22] memory: tegra30-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko
2020-03-30  1:08 ` [PATCH v2 17/22] memory: tegra30-emc: Register as interconnect provider Dmitry Osipenko
2020-04-13 12:44   ` Georgi Djakov
2020-04-13 15:18     ` Dmitry Osipenko
2020-03-30  1:09 ` [PATCH v2 18/22] drm/tegra: dc: Support memory bandwidth management Dmitry Osipenko
2020-03-30  1:09 ` [PATCH v2 19/22] drm/tegra: dc: Tune up high priority request controls for Tegra20 Dmitry Osipenko
2020-03-30  1:09 ` [PATCH v2 20/22] drm/tegra: dc: Extend debug stats with total number of events Dmitry Osipenko
2020-03-30  1:09 ` [PATCH v2 21/22] ARM: tegra: Enable interconnect API in tegra_defconfig Dmitry Osipenko
2020-03-30  1:09 ` [PATCH v2 22/22] ARM: multi_v7_defconfig: Enable interconnect API Dmitry Osipenko

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200330010904.27643-12-digetx@gmail.com \
    --to=digetx@gmail.com \
    --cc=a.swigon@samsung.com \
    --cc=devicetree@vger.kernel.org \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=georgi.djakov@linaro.org \
    --cc=jonathanh@nvidia.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pm@vger.kernel.org \
    --cc=linux-tegra@vger.kernel.org \
    --cc=robh+dt@kernel.org \
    --cc=thierry.reding@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox