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[84.3.50.134]) by smtp.gmail.com with ESMTPSA id u13sm6949379wru.88.2020.04.02.02.51.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 02:51:27 -0700 (PDT) Date: Thu, 2 Apr 2020 11:51:26 +0200 From: Ingo Molnar To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, Thomas Gleixner , Borislav Petkov , Peter Zijlstra , Andrew Morton Subject: [GIT PULL] x86 fix Message-ID: <20200402095125.GA21592@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Linus, Please pull the latest x86/urgent git tree from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-urgent-2020-04-02 # HEAD: 1651e700664b4597ddf4f8adfe435252a0d11277 x86: Fix bitops.h warning with a moved cast A single fix addressing Sparse warnings. is changed non-trivially to avoid the warnings, but generated code is not supposed to be affected. Hopefully I got the Git tagging and the scripting around it right. :-) The only slightly annoying part for the scripting was to extract the contents of the signed tag into the draft email, which I did with this rather inelegant hack: git tag -l --format='%(contents)' $TAG | gawk '/-----BEGIN PGP SIGNATURE-----/{exit;}//{print $0;}' | head -n -1 ... but I couldn't find a better way. I suspect Git is trying to gently tell me that I should be using 'git request-pull' instead of rolling my own, I guess? ;-) Thanks, Ingo ------------------> Jesse Brandeburg (1): x86: Fix bitops.h warning with a moved cast arch/x86/include/asm/bitops.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h index 062cdecb2f24..53f246e9df5a 100644 --- a/arch/x86/include/asm/bitops.h +++ b/arch/x86/include/asm/bitops.h @@ -54,7 +54,7 @@ arch_set_bit(long nr, volatile unsigned long *addr) if (__builtin_constant_p(nr)) { asm volatile(LOCK_PREFIX "orb %1,%0" : CONST_MASK_ADDR(nr, addr) - : "iq" ((u8)CONST_MASK(nr)) + : "iq" (CONST_MASK(nr) & 0xff) : "memory"); } else { asm volatile(LOCK_PREFIX __ASM_SIZE(bts) " %1,%0" @@ -74,7 +74,7 @@ arch_clear_bit(long nr, volatile unsigned long *addr) if (__builtin_constant_p(nr)) { asm volatile(LOCK_PREFIX "andb %1,%0" : CONST_MASK_ADDR(nr, addr) - : "iq" ((u8)~CONST_MASK(nr))); + : "iq" (CONST_MASK(nr) ^ 0xff)); } else { asm volatile(LOCK_PREFIX __ASM_SIZE(btr) " %1,%0" : : RLONG_ADDR(addr), "Ir" (nr) : "memory");