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Sat, 04 Apr 2020 18:28:50 -0700 (PDT) Received: from rob-hp-laptop ([64.188.179.250]) by smtp.gmail.com with ESMTPSA id k81sm4425517ilf.44.2020.04.04.18.28.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Apr 2020 18:28:49 -0700 (PDT) Received: (nullmailer pid 18915 invoked by uid 1000); Sun, 05 Apr 2020 01:28:47 -0000 Date: Sat, 4 Apr 2020 19:28:47 -0600 From: Rob Herring To: Adam Ford Cc: devicetree@vger.kernel.org, aford@beaconembedded.com, charles.stevens@logicpd.com, Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [RFC] clk: vc5: Add bindings for output configurations Message-ID: <20200405012847.GA5234@bogus> References: <20200326213251.54457-1-aford173@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200326213251.54457-1-aford173@gmail.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 26, 2020 at 04:32:51PM -0500, Adam Ford wrote: > The Versaclock can be purchased in a non-programmed configuration. > If that is the case, the driver needs to configure the chip to > output the correct signal type, voltage and slew. > > This RFC is proposing an additional binding to allow non-programmed > chips to be configured beyond their default configuration. > > Signed-off-by: Adam Ford > > diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt > index 05a245c9df08..4bc46ed9ba4a 100644 > --- a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt > +++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt > @@ -30,6 +30,25 @@ Required properties: > - 5p49v5933 and > - 5p49v5935: (optional) property not present or "clkin". > > +For all output ports, an option child node can be used to specify: > + > +- mode: can be one of > + - LVPECL: Low-voltage positive/psuedo emitter-coupled logic > + - CMOS > + - HCSL > + - LVDS: Low voltage differential signal > + > +- voltage-level: can be one of the following microvolts > + - 1800000 > + - 2500000 > + - 3300000 > +- slew: Percent of normal, can be one of > + - P80 > + - P85 > + - P90 > + - P100 > + > + > ==Mapping between clock specifier and physical pins== > > When referencing the provided clock in the DT using phandle and > @@ -62,6 +81,8 @@ clock specifier, the following mapping applies: > > ==Example== > > +#include > + > /* 25MHz reference crystal */ > ref25: ref25m { > compatible = "fixed-clock"; > @@ -80,6 +101,13 @@ i2c-master-node { > /* Connect XIN input to 25MHz reference */ > clocks = <&ref25m>; > clock-names = "xin"; > + > + ports@1 { 'ports' is already taken as a node name. > + reg = <1>; What do the reg value signify? > + mode = ; > + pwr_sel = <1800000>; Not documented. Don't use '-' in property names. > + slew = ; > + }; > }; > }; > > -- > 2.25.1 >