From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91A8AC2BB86 for ; Fri, 10 Apr 2020 17:00:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 696D0207FF for ; Fri, 10 Apr 2020 17:00:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="Gug0M9Uy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726678AbgDJRAp (ORCPT ); Fri, 10 Apr 2020 13:00:45 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:58712 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726203AbgDJRAp (ORCPT ); Fri, 10 Apr 2020 13:00:45 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Type:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=oUKFqLg3+HDFm2vs2QWf5wGOnTF90+YW2FpbPNodGzs=; b=Gug0M9UyuSpEBsOoExHvkg79nj RraZD7s/HpjWHeZhbOm1BTN9DBDiI2Isn1+bvmxmTSDIrbX8CQXtqQh3YB3OwGB7+l/o9XGoDoWCC pRm39IUagOU54lOG36W8XUoJ/UXPMnC67Qf+gqMTWNVdbv/3Bt5Fjum7MZRraqCdCQCI=; Received: from andrew by vps0.lunn.ch with local (Exim 4.93) (envelope-from ) id 1jMx0O-001zrZ-H4; Fri, 10 Apr 2020 18:59:48 +0200 Date: Fri, 10 Apr 2020 18:59:48 +0200 From: Andrew Lunn To: Jian Cai Cc: Linus Walleij , Peter.Smith@arm.com, stefan@agner.ch, David Howells , Mauro Carvalho Chehab , manojgupta@google.com, Benjamin Gaignard , "Joel Fernandes (Google)" , clang-built-linux@googlegroups.com, ilie.halip@gmail.com, Masahiro Yamada , Russell King , Krzysztof Kozlowski , Bartosz Golaszewski , samitolvanen@google.com, "Eric W. Biederman" , Arnd Bergmann , "Steven Rostedt (VMware)" , jiancai@google.com, Doug Anderson , Dan Williams , linux-arm-kernel@lists.infradead.org, Greg Kroah-Hartman , ndesaulniers@google.com, linux-kernel@vger.kernel.org, Patrick Bellasi , Masami Hiramatsu , Tejun Heo , Andrew Morton Subject: Re: [PATCH] ARM: do not assemble iwmmxt.S with LLVM toolchain Message-ID: <20200410165948.GD448831@lunn.ch> References: <20200409232728.231527-1-caij2003@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200409232728.231527-1-caij2003@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 09, 2020 at 04:27:26PM -0700, Jian Cai wrote: > iwmmxt.S contains XScale instructions Dumb question.... Are these Xscale instructions? My understanding is that they are an instruction set of their own, implementing something similar to IA-32 MMX. Would it be more accurate to say CLANG does not support the iwmmxt instruction set? Andrew