Re: [PATCH v2 10/10] PCIe: qcom: add Force GEN1 support

Stanimir Varbanov
2020-04-03T09:01:09Z

Hi Ansuel,

On 4/2/20 3:11 PM, Ansuel Smith wrote:
> From: Sham Muthayyan <smuthayy@codeaurora.org>
>
> Add Force GEN1 support needed in some ipq806x board
> that needs to limit some pcie line to gen1 for some
> hardware limitation.
> This is set by the max-link-speed dts entry and needed
> by some soc based on ipq806x. (for example Netgear R7800
> router)
>
> Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 8047ac7dc8c7..2212e9498b91 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -27,6 +27,7 @@
> #include <linux/slab.h>
> #include <linux/types.h>
>
> +#include "../../pci.h"

This looks suspiciously (even ugly), but I saw that the other users of
of_pci_get_max_link_speed is doing the same.

Bjorn H. : do you know why the prototype is there? Perhaps it must be in
linux/of_pci.h.

> #include "pcie-designware.h"
>
> #define PCIE20_PARF_SYS_CTRL 0x00
> @@ -99,6 +100,8 @@
> #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
> #define SLV_ADDR_SPACE_SZ 0x10000000
>
> +#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0

tabs instead of spaces and hex numbers should be lower-case

> +
> #define DEVICE_TYPE_RC 0x4
>
> #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
> @@ -199,6 +202,7 @@ struct qcom_pcie {
> struct phy *phy;
> struct gpio_desc *reset;
> const struct qcom_pcie_ops *ops;
> + bool force_gen1;

could you rename this and make it int:

int gen;

> };
>
> #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
> @@ -441,6 +445,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
>
> /* wait for clock acquisition */
> usleep_range(1000, 1500);

add a blank line here

> + if (pcie->force_gen1) {

if (pcie->gen == 1) {

> + writel_relaxed((readl_relaxed(
> + pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2) | 1),
> + pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
> + }

why you are using writel/readl_relaxed ?

Also could you split the line to two:

val = read()
write(val | 1, address)

>
>
> /* Set the Max TLP size to 2K, instead of using default of 4K */
> @@ -1440,6 +1449,10 @@ static int qcom_pcie_probe(struct platform_device *pdev)
> goto err_pm_runtime_put;
> }
>
> + ret = of_pci_get_max_link_speed(pdev->dev.of_node);> + if (ret == 1)
> + pcie->force_gen1 = true;

drop this, handle ret < 0 and default to generation 2

pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node);
if (pcie->gen < 0)
pcie->gen = 2;

> +
> res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
> pcie->parf = devm_ioremap_resource(dev, res);
> if (IS_ERR(pcie->parf)) {
>

--
regards,
Stan