Re: [PATCH v3 2/2] devicetree: bindings: phy: Document ipq806x dwc3 qcom phy

Rob Herring
2020-04-28T15:58:50Z

On Wed, Apr 15, 2020 at 11:07:27PM +0200, Ansuel Smith wrote:
> Document dwc3 qcom phy hs and ss phy bindings needed to correctly
> inizialize and use usb on ipq806x SoC.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
> v3:
> * Use explicit reg instead of regmap
>
> .../bindings/phy/qcom,ipq806x-usb-phy-hs.yaml | 58 +++++++++++++++
> .../bindings/phy/qcom,ipq806x-usb-phy-ss.yaml | 70 +++++++++++++++++++
> 2 files changed, 128 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml
> create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml
> new file mode 100644
> index 000000000000..c019de7478e3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-hs.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm ipq806x usb DWC3 HS PHY CONTROLLER
> +
> +maintainers:
> + - Ansuel Smith <ansuelsmth@gmail.com>
> +
> +description:
> + DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
> + controllers used in ipq806x. Each DWC3 PHY controller should have its
> + own node.
> +
> +properties:
> + compatible:
> + const: qcom,ipq806x-usb-phy-hs
> +
> + "#phy-cells":
> + const: 0
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 1
> + maxItems: 2
> +
> + clock-names:
> + minItems: 1
> + maxItems: 2
> + description: |
> + - "ref" Is required
> + - "xo" Optional external reference clock
> + items:
> + - const: ref
> + - const: xo
> +
> +required:
> + - compatible
> + - "#phy-cells"
> + - reg
> + - clocks
> + - clock-names
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
> +
> + hs_phy_0: phy@110f8800 {
> + compatible = "qcom,ipq806x-usb-phy-hs";
> + reg = <0x110f8800 0x30>;
> + clocks = <&gcc USB30_0_UTMI_CLK>;
> + clock-names = "ref";
> + #phy-cells = <0>;
> + };
> diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml
> new file mode 100644
> index 000000000000..29a7d3aed289
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-ss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm ipq806x usb DWC3 SS PHY CONTROLLER
> +
> +maintainers:
> + - Ansuel Smith <ansuelsmth@gmail.com>
> +
> +description:
> + DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
> + controllers used in ipq806x. Each DWC3 PHY controller should have its
> + own node.
> +
> +properties:
> + compatible:
> + const: qcom,ipq806x-usb-phy-ss
> +
> + "#phy-cells":
> + const: 0
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 1
> + maxItems: 2
> +
> + clock-names:
> + minItems: 1
> + maxItems: 2
> + description: |
> + - "ref" Is required
> + - "xo" Optional external reference clock
> + items:
> + - const: ref
> + - const: xo
> +
> + rx_eq:

qcom,rx-eq

> + maxItems: 1

Is this an array?

> + description: Override value for rx_eq. Default is 4.
> +
> + tx_deamp_3_5db:

qcom,tx-deamp-3-5db

> + maxItems: 1
> + description: Override value for transmit preemphasis. Default is 23.

default: 23

> +
> + mpll:

qcom,mpll

> + maxItems: 1
> + description: Override value for mpll. Default is 0.

Constraints?

default: 0

> +
> +required:
> + - compatible
> + - "#phy-cells"
> + - reg
> + - clocks
> + - clock-names
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
> +
> + ss_phy_0: phy@110f8830 {
> + compatible = "qcom,ipq806x-usb-phy-ss";
> + reg = <0x110f8830 0x30>;
> + clocks = <&gcc USB30_0_MASTER_CLK>;
> + clock-names = "ref";
> + #phy-cells = <0>;
> + };
> --
> 2.25.1
>