From: Mark Brown <broonie@kernel.org>
To: Kamal Dasu <kdasu.kdev@gmail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>,
bcm-kernel-feedback-list <bcm-kernel-feedback-list@broadcom.com>,
linux-spi <linux-spi@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [Patch v2 3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset
Date: Mon, 20 Apr 2020 16:17:48 +0100 [thread overview]
Message-ID: <20200420151748.GE10045@sirena.org.uk> (raw)
In-Reply-To: <CAC=U0a1mOWo3ucMJ7x5wuWQ44NRA2+Dj6fKAi1dbevNaxcYJzA@mail.gmail.com>
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On Mon, Apr 20, 2020 at 11:12:21AM -0400, Kamal Dasu wrote:
> Yes missed this one.
> Should I send a v3 of the entire set.
Yes.
Please don't top post, reply in line with needed context. This allows
readers to readily follow the flow of conversation and understand what
you are talking about and also helps ensure that everything in the
discussion is being addressed.
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next prev parent reply other threads:[~2020-04-20 15:17 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20200419192339.32023-1-kdasu.kdev@gmail.com>
2020-04-19 19:23 ` [Patch v2 1/9] spi: bcm-qspi: Handle clock probe deferral Kamal Dasu
2020-04-19 19:23 ` [Patch v2 2/9] dt: bindings: spi: Add support for mspi on brcmstb SoCs Kamal Dasu
2020-04-19 19:23 ` [Patch v2 3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset Kamal Dasu
2020-04-19 19:44 ` Florian Fainelli
2020-04-20 15:12 ` Kamal Dasu
2020-04-20 15:17 ` Mark Brown [this message]
2020-04-19 19:23 ` [Patch v2 4/9] spi: bcm-qspi: Drive MSPI peripheral SSb pin on cs_change Kamal Dasu
2020-04-19 19:23 ` [Patch v2 5/9] spi: bcm-qspi: when tx/rx buffer is NULL set to 0 Kamal Dasu
2020-04-19 19:23 ` [Patch v2 6/9] spi: bcm-qspi: Make PM suspend/resume work with SCMI clock management Kamal Dasu
2020-04-19 19:23 ` [Patch v2 7/9] spi: bcm-qspi: Use fastbr setting to allow faster MSPI speeds Kamal Dasu
2020-04-19 19:23 ` [Patch v2 8/9] spi: bcm-qspi: add support for MSPI sys clk 108Mhz Kamal Dasu
2020-04-19 19:23 ` [Patch v2 9/9] spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllers Kamal Dasu
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