Re: [PATCH v1 1/6] arm64: Detect the ARMv8.4 TTL feature

Zhenyu Ye
2020-04-22T02:13:55Z

On 2020/4/22 1:16, Christoph Hellwig wrote:
> On Tue, Apr 21, 2020 at 07:13:28PM +0200, Peter Zijlstra wrote:
>> On Tue, Apr 21, 2020 at 09:53:46AM -0700, Christoph Hellwig wrote:
>>> On Fri, Apr 03, 2020 at 05:00:43PM +0800, Zhenyu Ye wrote:
>>>> From: Marc Zyngier <maz@kernel.org>
>>>>
>>>> In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL
>>>> feature allows TLBs to be issued with a level allowing for quicker
>>>> invalidation.
>>>
>>> What does "issued with a level" mean?
>>
>> What I understood it to be is page-size based on page-table hierarchy.
>> Just like we have on x86, 4k, 2m, 1g etc..
>>
>> So where x86 INVLPG will tear down any sized page for the address given,
>> you can now day, kill me the PMD level translation for @addr.
>>
>> Power9 radix also has things like this.
>
> Maybe this needs to be spelled out a little more? The current commit
> log sounds like paper generated by a neural network.
>

Emm... This patch was synchronized from Marc's NV series [1].
"issued with a level" means the TLBs now can get which levels of
page tables the @addr is in. You can also understand it as
page-size as Peter said above, just like pud, pmd, pte...

Anyway, I will explain this in more detail.

Thanks,
Zhenyu