Re: [PATCH RFC 07/15] Documentation: Interrupt Message store

Jason Gunthorpe
2020-04-23T20:05:54Z

On Tue, Apr 21, 2020 at 04:34:30PM -0700, Dave Jiang wrote:

> diff --git a/Documentation/ims-howto.rst b/Documentation/ims-howto.rst
> new file mode 100644
> index 000000000000..a18de152b393
> +++ b/Documentation/ims-howto.rst
> @@ -0,0 +1,210 @@
> +.. SPDX-License-Identifier: GPL-2.0
> +.. include:: <isonum.txt>
> +
> +==========================
> +The IMS Driver Guide HOWTO
> +==========================
> +
> +:Authors: Megha Dey
> +
> +:Copyright: 2020 Intel Corporation
> +
> +About this guide
> +================
> +
> +This guide describes the basics of Interrupt Message Store (IMS), the
> +need to introduce a new interrupt mechanism, implementation details of
> +IMS in the kernel, driver changes required to support IMS and the general
> +misconceptions and FAQs associated with IMS.

I'm not sure why we need to call this IMS in kernel documentat? I know
Intel is using this term, but this document is really only talking
about extending the existing platform_msi stuff, which looks pretty
good actually.

A lot of this is good for the cover letter..

> +Implementation of IMS in the kernel
> +===================================
> +
> +The Linux kernel today already provides a generic mechanism to support
> +non-PCI compliant MSI interrupts for platform devices (platform-msi.c).
> +To support IMS interrupts, we create a new IMS IRQ domain and extend the
> +existing infrastructure. Dynamic allocation of IMS vectors is a requirement
> +for devices which support Scalable I/O Virtualization. A driver can allocate
> +and free vectors not just once during probe (as was the case with MSI/MSI-X)
> +but also in the post probe phase where actual demand is available. Thus, a
> +new API, platform_msi_domain_alloc_irqs_group is introduced which drivers
> +using IMS would be able to call multiple times. The vectors allocated each
> +time this API is called are associated with a group ID. To free the vectors
> +associated with a particular group, the platform_msi_domain_free_irqs_group
> +API can be called. The existing drivers using platform-msi infrastructure
> +will continue to use the existing alloc (platform_msi_domain_alloc_irqs)
> +and free (platform_msi_domain_free_irqs) APIs and are assigned a default
> +group ID of 0.
> +
> +Thus, platform-msi.c provides the generic methods which can be used by any
> +non-pci MSI interrupt type while the newly created ims-msi.c provides IMS
> +specific callbacks that can be used by drivers capable of generating IMS
> +interrupts.

How exactly is an IMS interrupt is different from a platform msi?

It looks like it is just some thin wrapper around msi_domain - what is
it for?

> +FAQs and general misconceptions:
> +================================
> +
> +** There were some concerns raised by Thomas Gleixner and Marc Zyngier
> +during Linux plumbers conference 2019:
> +
> +1. Enumeration of IMS needs to be done by PCI core code and not by
> + individual device drivers:
> +
> + Currently, if the kernel needs a generic way to discover IMS capability
> + without host driver dependency, the PCIE Designated Vendor specific
> +
> + However, we cannot have a standard way of enumerating the IMS size
> + because for context based devices, the interrupt message is part of
> + the context itself which is managed entirely by the driver. Since
> + context creation is done on demand, there is no way to tell during boot
> + time, the maximum number of contexts (and hence the number of interrupt
> + messages)that the device can support.

FWIW, I agree with this.

Like platform-msi, IMS should be controlled entirely by the driver.

> +2. Why is Intel designing a new interrupt mechanism rather than extending
> + MSI-X to address its limitations? Isn't 2048 device interrupts enough?
> +
> + MSI-X has a rigid definition of one-table and on-device storage and does
> + not provide the full flexibility required for future multi-tile
> + accelerator designs.
> + IMS was envisioned to be used with large number of ADIs in devices where
> + each will need unique interrupt resources. For example, a DSA shared
> + work queue can support large number of clients where each client can
> + have its own interrupt. In future, with user interrupts, we expect the
> + demand for messages to increase further.

Generally agree

> +Device Driver Changes:
> +=====================
> +
> +1. platform_msi_domain_alloc_irqs_group (struct device *dev, unsigned int
> + nvec, const struct platform_msi_ops *platform_ops, int *group_id)
> + to allocate IMS interrupts, where:
> +
> + dev: The device for which to allocate interrupts
> + nvec: The number of interrupts to allocate
> + platform_ops: Callbacks for platform MSI ops (to be provided by driver)
> + group_id: returned by the call, to be used to free IRQs of a certain type
> +
> + eg: static struct platform_msi_ops ims_ops = {
> + .irq_mask = ims_irq_mask,
> + .irq_unmask = ims_irq_unmask,
> + .write_msg = ims_write_msg,
> + };
> +
> + int group;
> + platform_msi_domain_alloc_irqs_group (dev, nvec, platform_ops, &group)
> +
> + where, struct platform_msi_ops:
> + irq_mask: mask an interrupt source
> + irq_unmask: unmask an interrupt source
> + irq_write_msi_msg: write message content
> +
> + This API can be called multiple times. Every time a new group will be
> + associated with the allocated vectors. Group ID starts from 0.

Need much more closer look, but this seems conceptually fine to me.

As above the API here is called platform_msi - which seems good to
me. Again not sure why the word IMS is needed

Jason