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From: Mark Brown <broonie@kernel.org>
To: Dilip Kota <eswara.kota@linux.intel.com>
Cc: robh@kernel.org, linux-spi@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	daniel.schwierzeck@gmail.com, hauke@hauke-m.de,
	andriy.shevchenko@intel.com, cheol.yong.kim@intel.com,
	chuanhua.lei@linux.intel.com, qi-ming.wu@intel.com
Subject: Re: [PATCH 1/4] spi: lantiq: Synchronize interrupt handlers and transfers
Date: Mon, 27 Apr 2020 14:45:55 +0100	[thread overview]
Message-ID: <20200427134555.GC4383@sirena.org.uk> (raw)
In-Reply-To: <616a5419-add3-085e-32dc-c83d9d975725@linux.intel.com>

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On Mon, Apr 27, 2020 at 02:01:29PM +0800, Dilip Kota wrote:
> On 4/24/2020 7:25 PM, Mark Brown wrote:
> > On Fri, Apr 24, 2020 at 06:42:30PM +0800, Dilip Kota wrote:

> > > Synchronize tx, rx and error interrupts by registering to the
> > > same interrupt handler. Interrupt handler will recognize and process
> > > the appropriate interrupt on the basis of interrupt status register.
> > > Also, establish synchronization between the interrupt handler and
> > > transfer operation by taking the locks and registering the interrupt
> > > handler as thread IRQ which avoids the bottom half.
> > > Fixes the wrongly populated interrupt register offsets too.

> > This sounds like at least three different changes mixed together in one
> > commit, it makes it quite hard to tell what's going on.  If nothing else
> > the conversion from a workqueue to threaded interrupts should probably
> > be split out from merging the interrupts.

> While preparing the patches, i got puzzled to go with separate patches (for
> threaded interrupts, unified interrupt handler and fixing the register
> offset) or as a single patch!!.

> Finally i choose to go with single patch, because establishing
> synchronization is the major reason for this change, for that reason
> threaded interrupts and unified interrupts changes are done. And the fixing
> offset is a single line change, so included in this patch itself. And, on a
> lighter note, the whole patch is coming under 45 lines of code changes.
> Please let me know your view.

The single line change to fix the offset sounds like an especially good
candidate for splitting out as a separate patch.  It's not really about
the number of lines but rather complexity.

> > > -static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data)
> > > +static irqreturn_t lantiq_ssc_err_interrupt(struct lantiq_ssc_spi *spi)
> > >   {
> > > -	struct lantiq_ssc_spi *spi = data;
> > >   	u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
> > > -	if (!(stat & LTQ_SPI_STAT_ERRORS))
> > > -		return IRQ_NONE;
> > > -

> > Why drop this?

> lantiq_ssc_err_interrupt() getting called, only if LTQ_SPI_IRNEN_E is set in
> the interrupt status register.
> Once the 'LTQ_SPI_IRNEN_E' bit is set, there is no chance of all error bits
> being unset in the SPI_STAT register, so the 'if condition' will never be
> successful. Hence dropped it.

So this is another separate change and TBH it doesn't seem like a huge
win in that it's still potentially adding a bit of robustness.

> > It's not clear to me that it's a benefit to combine all the interrupts
> > unconditionally - obviously where they're shared we need to but could
> > that be accomplished with IRQF_SHARED and even if it can't it seems like
> > something conditional would be better.

> Lets take a case where Tx/Rx transfer interrupt got triggered and followed
> by error interrupt(before finishing the tx/rx interrupt execution) which is
> very less likely to occur, unified interrupt handler establishes
> synchronization.
> Comparatively, unified interrupt handler is better for adding support to the
> latest SoCs on which SPI have single interrupt line for tx,rx and errors.
> On basis of these two points i felt to go with unified interrupt handler.

Does the mutex not do this regardless of how the interrupt handlers are
wired up?

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  reply	other threads:[~2020-04-27 13:46 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-24 10:42 [PATCH 0/4] spi: lantiq: Synchronize interrupts, transfers and add new features Dilip Kota
2020-04-24 10:42 ` [PATCH 1/4] spi: lantiq: Synchronize interrupt handlers and transfers Dilip Kota
2020-04-24 11:25   ` Mark Brown
2020-04-27  6:01     ` Dilip Kota
2020-04-27 13:45       ` Mark Brown [this message]
2020-04-28  5:39         ` Dilip Kota
2020-04-28 10:00           ` Mark Brown
2020-04-29  7:20             ` Dilip Kota
2020-04-29 12:27               ` Mark Brown
2020-04-27 21:52   ` Hauke Mehrtens
2020-04-28  6:03     ` Dilip Kota
2020-04-28 11:10   ` Daniel Schwierzeck
2020-04-28 11:30     ` Hauke Mehrtens
2020-04-29  8:22       ` Dilip Kota
2020-04-29  8:20     ` Dilip Kota
2020-04-29 12:13       ` Mark Brown
2020-05-04 10:15         ` Dilip Kota
2020-05-05 11:23           ` Mark Brown
2020-05-06  7:40             ` Dilip Kota
2020-07-16  9:36               ` Dilip Kota
2020-04-24 10:42 ` [PATCH 2/4] spi: lantiq: Dynamic configuration of interrupts and FIFO size Dilip Kota
2020-04-24 10:42 ` [PATCH 3/4] dt-bindings: spi: Add support to Lightning Mountain SoC Dilip Kota
2020-05-11 21:22   ` Rob Herring
2020-04-24 10:42 ` [PATCH 4/4] spi: lantiq: " Dilip Kota

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