Re: [PATCH v4 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC

Boris Brezillon
2020-04-30T13:01:33Z

On Thu, 30 Apr 2020 14:36:00 +0200
Boris Brezillon <boris.brezillon@collabora.com> wrote:

> On Thu, 30 Apr 2020 17:07:03 +0800
> "Ramuthevar, Vadivel MuruganX"
> <vadivel.muruganx.ramuthevar@linux.intel.com> wrote:
>
> > >>> The question is, is it the same value we have in nand_pa or it is
> > >>> different?
> > >>>
> > >> Different address which is 0xE1400000 NAND_BASE_PHY address.
> > >
> > > Then why didn't you tell me they didn't match when I suggested to pass
> >
> > sorry, because you keep asking nand_pa after that only I realized that.
> >
> > > nand_pa? So now the question is, what does this address represent?
> >
> > EBU-MODULE
> > _________ _______________________
> > | | | |NAND CTRL |
> > | FPI BUS |==>| CS0(0x174) | 0xE100 ( 0xE14/0xE1C) NAND_PHY_BASE
> > |_________| |_CS1(0x17C)_|__________ |
> >
> > EBU_CONRTROLLER_BASE : 0xE0F0_0000
> > HSNAND_BASE: 0xE100_0000
> > NAND_CS0: 0xE140_0000
> > NAND_CS1: 0xE1C0_0000
> >
> > MEM_REGION_BASE_CS0: 0x17400 (internal to ebu controller )
> > MEM_REGION_BASE_CS1: 0x17C00
> >
>
> Hm, I wonder if we shouldn't use a 'ranges' property to describe this
> address translation. Something like
>
> ebu@xxx {
> ranges = <0x17400000 0xe1400000 0x1000>,
> <0x17c00000 0xe1c00000 0x1000>;
> reg = <0x17400000>, <0x17c00000>;
> reg-names = "cs-0", "cs-1";
> }
>
> The translated address (0xE1X00000) will be available in res->start,
> and the non-translated one (0x17X00000) can be retrieved with
> of_get_address(). All you'd have to do then would be calculate the
> mask:
>
> mask = (translated_address & original_address) >> 22;
> num_comp_bits = fls(mask);
> WARN_ON(mask != GENMASK(num_comp_bits - 1, 0));
>
> Which allows you to properly set the ADDR_SEL() register without
> relying on some hardcoded values:
>
> writel(original_address | EBU_ADDR_SEL_REGEN |
> EBU_ADDR_COMP_BITS(num_comp_bits),
> ebu_host->ebu + EBU_ADDR_SEL(csid));
>
> That's quite important if we want to merge the xway NAND driver with
> this one.

Looks like the translation is done at the FPI bus declaration level (see
[1]). We really need to see the big picture to take a wise decision
about the bindings. Would you mind pasting your dsti/dts files
somewhere? It feels like the NAND controller is a sub-part of a more
generic 'memory' controller, in which case the NAND controller should be
declared as a child of this generic memory bus (called localbus in [1],
but maybe EBU is more accurate).

[1]https://github.com/xieyaxiongfly/Atheros_CSI_tool_OpenWRT_src/blob/master/target/linux/lantiq/files-4.14/arch/mips/boot/dts/vr9.dtsi#L162