From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA803C47256 for ; Wed, 6 May 2020 17:05:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B08B92080D for ; Wed, 6 May 2020 17:05:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Rgc7eSgJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729886AbgEFRFN (ORCPT ); Wed, 6 May 2020 13:05:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729414AbgEFRFM (ORCPT ); Wed, 6 May 2020 13:05:12 -0400 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3145DC061A0F; Wed, 6 May 2020 10:05:12 -0700 (PDT) Received: by mail-wr1-x441.google.com with SMTP id e16so3076809wra.7; Wed, 06 May 2020 10:05:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=3x0uOI1BgySr4JAhryI/+ahsj3uZRjc+tpO/+35ZZwM=; b=Rgc7eSgJ+cqlaFrG9r5KSSCvjShNUu/8DSZbN8gI8P/1tuUWmgS+GTNh8XOlgSpfIb hI90vv6rQOPGLNIPE3iDemjFkSKLOa0yiT1y2J8Fa93JPIA+MLml+Xwy7JfTjPRKetQg 1qclsBZFdjsCDg9AjerK1wjbNvXTaxS/y9YlGx1ryJJ4FR9MrvtXZjk0uci26KAuNsDO K08kZWBfXsZXqBUGgnsdj0GXTziUvmI0Qp8Rx8QZJJZoTJA+1Fgww+c7hs2l1/Xwfy8H vXvFD0gXJMEvinG6pZa+W8CIdWs9dCAWwUSFrc2aCGGyLz1PK7RSn2GPW6RKoTI8CABg qdEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=3x0uOI1BgySr4JAhryI/+ahsj3uZRjc+tpO/+35ZZwM=; b=BaUru9fQk80BQukvkSFKzweLUZqZo6A9p2vSYgH4F8MA5ONCfs4OYzJCAn12PNFgIE 3LKdKSVXZeCR/qGrqyDkN3dFAoLPgxeKnmEPTqrKaeNSOjsdkgj401+N8PzLXk7fhGwB ckZdgx0EOyTYS5EhxKbqWMm6OVQ5uXcyrdwdFClPZH2dYClvTzQJ7eecZTvjM2wj/6QX 85ixt61zIet5xxexkxfHhpREgiG7cxqtxSpTCUEoOUwoZ3eNGHRv6Zc+jG/EWibr6RHN Mw1z4fNvTcCJ3mPGRkcROQumkZTe3FjBlpLFSUZFiJd6AUAjOxSw1HbujQMdK1mXfy+f /A/g== X-Gm-Message-State: AGi0PubTvAnZ64huk+nU4313E2eBynLajgop9HZvlgkmWTM0++pfWosQ T608kS2lQ90wwki888Bl4oqfyH8P+0E= X-Google-Smtp-Source: APiQypIC+CI7iz0lwgrPCobaoNgtlY8ZcMXxo8iAjROexajFRgzSeVNvOyjJva4yc4ljkdQ68oMxBg== X-Received: by 2002:a5d:438c:: with SMTP id i12mr10557540wrq.14.1588784710844; Wed, 06 May 2020 10:05:10 -0700 (PDT) Received: from localhost (p2E5BE57B.dip0.t-ipconnect.de. [46.91.229.123]) by smtp.gmail.com with ESMTPSA id 5sm3872042wmz.16.2020.05.06.10.05.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2020 10:05:09 -0700 (PDT) Date: Wed, 6 May 2020 19:05:08 +0200 From: Thierry Reding To: Dmitry Osipenko Cc: Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?B?TWljaGHFgiBNaXJvc8WCYXc=?= , Jasper Korten , David Heidelberg , linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v8 00/12] NVIDIA Tegra20 CPUFreq driver major update Message-ID: <20200506170508.GE2723987@ulmo> References: <20200319190229.32200-1-digetx@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="10jrOL3x2xqLmOsH" Content-Disposition: inline In-Reply-To: <20200319190229.32200-1-digetx@gmail.com> User-Agent: Mutt/1.13.1 (2019-12-14) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --10jrOL3x2xqLmOsH Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Mar 19, 2020 at 10:02:17PM +0300, Dmitry Osipenko wrote: > Hello, >=20 > This series moves intermediate-clk handling from tegra20-cpufreq into > tegra-clk driver. This allows us to switch to generic cpufreq-dt driver > which brings voltage scaling, per-hardware OPPs and Tegra30 support out > of the box. All boards need to adopt CPU OPPs in their device-trees in > order to get cpufreq support. >=20 > Changelog: >=20 > v8: - Rebased on a recent linux-next because Thierry merged the cpuidle > series first and now there is one minor conflict. >=20 > - Added tested-by from Nicolas Chauvet who was one of the first > testers of the series. >=20 > v7: - Added acks from Peter De Schrijver. >=20 > - Added tested-by from Marcel Ziswiler, Peter Geis, Jasper Korten and > David Heidelberg who tested these patches on Apalis/Colibri devboar= ds, > Ouya, TF300T and Nexus 7 devices respectively. >=20 > - Rebased series on top of recent linux-next. >=20 > v6: - Dropped "cpufreq: dt-platdev: Blacklist NVIDIA Tegra20 and Tegra30 = SoCs" > patch from the series since Viresh picked up that patch separately. >=20 > - Added two new patches to this series: >=20 > ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/= 124 > ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30 >=20 > Previously these patches were sent out separately from this series, > but it should be more consistent to include them into the series si= nce > they directly relate to enabling of the cpufreq driver on Tegra30. >=20 > v5: - The "Use generic cpufreq-dt driver (Tegra30 supported now)" patch > is separated now into two patches by factoring out the blacklisting > of cpufreq-dt-platdev into a standalone patch. This is done in a > response to request from Jon Hunter to fix the warning splats during > boot that are coming from OPP core because OPPs are unavailable. The > OPPs will become available once tegra20-cpufreq driver will be upda= ted > to support the cpufreq-dt. >=20 > v4: - Updated CCLK diagram in the "Add custom CCLK implementation" patch. >=20 > - is now included in the "Use generic cpufreq-dt driver" > patch, for consistency. >=20 > - Returned value of get_cpu_device() is now checked in the "Use gener= ic > cpufreq-dt driver" patch, for consistency as well. >=20 > v3: - The "Add custom CCLK implementation" patch was updated in accordance > to the comments from Peter De Schrijver. We will not use the clock > skipper. >=20 > - Re added OPPs for T30 Beaver board because Thierry has that board ;) >=20 > - Added r-b for the "DT binding" patch from Rob Herring. >=20 > v2: - Kept modularity of the tegra20-cpufreq as was requested by Viresh K= umar > in a review comment to v1. >=20 > - Added acks from Viresh Kumar. >=20 > - Added tested-by from Nicolas Chauvet to the "trimslice" patch. > Nicolas told me on IRC that it works fine. >=20 > - Fixed compilation of the "Add custom CCLK implementation" patch. The > error happened because v1 was based on top of yet unreviewed/unappl= ied > patch "clk: tegra: divider: Support enable-bit for Super clocks". > Thanks to Peter Geis for reporting the problem. >=20 > - Replaced Tegra30 "beaver" board with "cardhu-a04" because turned out > that's what NVIDIA uses in the testing farm. >=20 > Dmitry Osipenko (12): > clk: tegra: Add custom CCLK implementation > clk: tegra: pll: Add pre/post rate-change hooks > clk: tegra: cclk: Add helpers for handling PLLX rate changes > clk: tegra20: Use custom CCLK implementation > clk: tegra30: Use custom CCLK implementation Applied to for-5.8/clk. > ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124 > ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30 Applied to for-5.8/arm/core. > dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 Applied to for-5.8/dt-bindings. > cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported > now) Applied to for-5.8/cpufreq. > ARM: tegra: Create tegra20-cpufreq platform device on Tegra30 Applied to for-5.8/arm/core. > ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS > ARM: dts: tegra30: beaver: Add CPU Operating Performance Points Applied to for-5.8/arm/dt. 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